research-article

Re-examining the use of network-on-chip as test access mechanism

Authors:

Qiang XuAuthors Info & Claims

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

Pages 808 - 811

https://doi.org/10.1145/1403375.1403571

Published: 10 March 2008 Publication History

Abstract

Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this methodology obviously reduces the routing cost when compared to the case that dedicated test buses are introduced as TAMs, it is not clear whether it is beneficial in terms of other important factors that significantly affect test cost, e.g., testing time, test control complexity and test reliability. As a result, in this paper, we re-examine the issue of using NoC as TAM in order to facilitate designers to construct a cost-effective system test architecture based on their requirements.

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Cited By

Zhang YJi PZhu PPeng ZLi HJiang J(2023)Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-ChipJournal of Computer Science and Technology10.1007/s11390-022-2553-338:2(405-421)Online publication date: 30-Mar-2023
https://doi.org/10.1007/s11390-022-2553-3
Ren YLiu LYin SHan JWei S(2015)Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow AlgorithmACM Transactions on Reconfigurable Technology and Systems10.1145/27004178:3(1-24)Online publication date: 19-May-2015
https://dl.acm.org/doi/10.1145/2700417
Amory ALazzari CLubaszewski MMoraes F(2011)A new test scheduling algorithm based on Networks-on-Chip as Test Access MechanismsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.09.00871:5(675-686)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1016/j.jpdc.2010.09.008
Show More Cited By

Index Terms

Re-examining the use of network-on-chip as test access mechanism
1. Hardware

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cover image ACM Conferences

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

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DATE '08

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

Zhang YJi PZhu PPeng ZLi HJiang J(2023)Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-ChipJournal of Computer Science and Technology10.1007/s11390-022-2553-338:2(405-421)Online publication date: 30-Mar-2023
https://doi.org/10.1007/s11390-022-2553-3
Ren YLiu LYin SHan JWei S(2015)Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow AlgorithmACM Transactions on Reconfigurable Technology and Systems10.1145/27004178:3(1-24)Online publication date: 19-May-2015
https://dl.acm.org/doi/10.1145/2700417
Amory ALazzari CLubaszewski MMoraes F(2011)A new test scheduling algorithm based on Networks-on-Chip as Test Access MechanismsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.09.00871:5(675-686)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1016/j.jpdc.2010.09.008
Cota Éde Morais Amory ALubaszewski MCota Éde Morais Amory ASoares Lubaszewski M(2011)Advanced Approaches for NoC ReuseReliability, Availability and Serviceability of Networks-on-Chip10.1007/978-1-4614-0791-1_5(85-114)Online publication date: 14-Aug-2011
https://doi.org/10.1007/978-1-4614-0791-1_5
Cota Éde Morais Amory ALubaszewski MCota Éde Morais Amory ASoares Lubaszewski M(2011)Concluding RemarksReliability, Availability and Serviceability of Networks-on-Chip10.1007/978-1-4614-0791-1_10(195-200)Online publication date: 14-Aug-2011
https://doi.org/10.1007/978-1-4614-0791-1_10
Binzhang Fu Yinhe Han Huawei Li Xiaowei Li (2009)T²- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip2009 IEEE 8th International Conference on ASIC10.1109/ASICON.2009.5351598(91-96)Online publication date: Oct-2009
https://doi.org/10.1109/ASICON.2009.5351598
Huang LYuan FXu QFix L(2008)On reliable modular testing with vulnerable test access mechanismsProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391681(834-839)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391681

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