research-article

Parametric yield management for 3D ICs: Models and strategies for improvement

Authors:

R. Iris BaharAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 4, Issue 4

Article No.: 19, Pages 1 - 22

https://doi.org/10.1145/1412587.1412592

Published: 07 November 2008 Publication History

Abstract

Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2×, while simultaneously reducing the number of slow ICs by 29.4%. This leads to an improvement in performance by up to 6.45% and an increase of about 12.48% in total sales revenue using up-to-date market price models.

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Index Terms

Parametric yield management for 3D ICs: Models and strategies for improvement
1. Hardware
  1. Emerging technologies
  2. Hardware validation

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 4, Issue 4

October 2008

123 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/1412587

Issue’s Table of Contents

Copyright © 2008 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 November 2008

Accepted: 01 June 2008

Revised: 01 April 2008

Received: 01 November 2007

Published in JETC Volume 4, Issue 4

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Siavashi AMomtazpour M(2022)Yield-aware joint die packing, die matching and static thread mapping for hard real-time 3D embedded CMPsMicroprocessors & Microsystems10.1016/j.micpro.2022.10454392:COnline publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1016/j.micpro.2022.104543
Chien CLee PDou RChen YChen C(2017)Modeling collinear WATs for parametric yield enhancement in semiconductor manufacturing2017 13th IEEE Conference on Automation Science and Engineering (CASE)10.1109/COASE.2017.8256192(739-743)Online publication date: 20-Aug-2017
https://dl.acm.org/doi/10.1109/COASE.2017.8256192
Han KKahng ALi JFanucci LTeich J(2016)Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stackingProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971822(61-66)Online publication date: 14-Mar-2016
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