Article

Free access

Register requirements of pipelined processors

Authors:

William Mangione-Smith,

Santosh G. Abraham,

Edward S. DavidsonAuthors Info & Claims

ICS '92: Proceedings of the 6th international conference on Supercomputing

Pages 260 - 271

https://doi.org/10.1145/143369.143419

Published: 01 August 1992 Publication History

Abstract

To enable concurrent instruction execution, scientific computers generally rely on pipelining, which combines with faster system clocks to achieve greater throughput. Each concurrently executing instruction requires buffer space, usually implemented as a register, to receive its result. This paper focuses on the issue of how many registers are required to achieve optimal performance in pipelined scientific computers. Four machine models are considered: single, double, and triple issue scalar machines, and vector machines with various register lengths. A model is presented that accurately relates the register requirements for optimum performance cyclically scheduled loops with tree-dependence graphs to the degree of function unit pipelining, the instruction issue bandwidth, and code properties. A method for finding upper and lower bounds on the minimum register requirements is also presented.

The result of this work is a theory for assessing register requirements that can be used to reveal fundamental differences among machines within a space of architectural and implementation design choices. Some experimental data is also provided to support the theory.

References

[1]

M. J. Flynn, "Very High-Speed Computing Systems," Proc. IEEB, vol. 54, pp. 1901-1909, December 1966.

[2]

R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth, and P. K. Rodman, "A VLIW Architecture for a Trace Scheduling Compiler," in Proc. ASPLOS.II, pp. 180-192, 1982.

Digital Library

[3]

B. J. Smith, "Architecture and Applications of the HEP Multiprocessor Computer System," Real Time Signal Procesing IV, vol. 298, August 1981.

[4]

Y. N. Patt, W.-M. W. Hwu, and M. Shebanow, "HPS, a New Microarchitecture: Rationale and Introduction," in Proc. of 18th Microprogramming Workshop, 1985.

Digital Library

[5]

D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo, "IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM Journal of Research and Development, pp. 8-24, January 1967.

Digital Library

[6]

W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "Vector Register Design for Polycyclic Vector Scheduling," in Proc. Fourth Conference on Architectural ~upport for Programming Languages and Operating Systems, April 1991.

Digital Library

[7]

P. Y. Hsu, Highly Concurrent Scalar Processing. PAD thesis, Coordinated Science Laboratory Report ~CSG-49, University of Illinois at Urbana- Champaign, 1986.

Digital Library

[8]

R. F. Touzeau, "A Fortran Compiler for the FPS- 164 Scientific Computer," in Proc. A CM SIGPLAN '84 Syrup on Compiler Construction, pp. 48-57, June 1984.

Digital Library

[9]

J. H. Patel and E. S. Davidson, "Improving the Throughput of a Pipeline by Insertion of Delays," in Proc. Third Annual ISCA, pp. 159-164, 1976.

Digital Library

[10]

B. R. Ran, C. D. Glaeser, and R. L. Picard, "Efficient Code Generation for Horizontal Architectures: Compiler Techniques and Architectural Support," in Proc. Int. Symp. on Computer Architecture, pp. 295-304, 1982.

Digital Library

[11]

B. R. Ran, D. W. L. Yen, W. Yen, and R. A. Towle, "The Cydra 5 Departmental Supercomputer," IEEE Computer, pp. 12-35, 1989.

Digital Library

[12]

C. Eisenbeis, W. Jalby, and A. Lichnewsky, "Compile-Time Optimization of Memory and Register Usage on the Cray-2," in Proceedings of the Second Workshop on Languages and Compilers, Urbana llinois, August 1989.

Digital Library

[13]

M. Lam, A Systolic Array Optimizing Compiler. PAD thesis, Carnegie Mellon University, 1987.

Digital Library

[14]

M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP- Completeness. W. H. Freeman and Company, 1979.

Digital Library

[15]

J. E. Smith, "Decoupled Access/Execute Architecture Computer Architectures," A CM Transactions on Computer Systems, pp. 289-308, November 1984.

Digital Library

[16]

W. H. Mangione-Smith, S. G. Abraham, and E. S. Davidson, "A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-I," IEEE Computer, vol. 24, January 1991.

Digital Library

[17]

W. H. Mangione-Smith, Performance Bounds and Buffer Space Requirements for Concurrent Processors. PAD thesis, Univ. of Mich., EECS Dept., Univ. of Mich., Ann Arbor, MI, 1992.

Digital Library

Cited By

Eichenberger ADavidson EAbraham S(2016)Minimizing Register Requirements of a Modulo Schedule via Optimum Stage SchedulingInternational Journal of Parallel Programming10.1007/BF0335674424:2(103-132)Online publication date: 26-May-2016
https://doi.org/10.1007/BF03356744
Eichenberger ADavidson EAbraham S(2014)Optimum modulo schedules for minimum register requirementsACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667171(227-236)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667171
Eichenberger ADavidson EAbraham S(2014)Author retrospective for optimum modulo schedules for minimum register requirementsACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2591653(35-36)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2591653
Show More Cited By

Index Terms

Recommendations

The microprogramming of pipelined processors
ISCA '77: Proceedings of the 4th annual symposium on Computer architecture

A pipelined processor is one whose computational capabilities are divided into several sequential stages, each of which may be working with an independent set of data at the same instant of time. Such processors are capable of handling large streams of ...
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors

This paper proposes and evaluates software techniques that increase register file utilization for simultaneous multithreading (SMT) processors. SMT processors require large register files to hold multiple thread contexts that can issue instructions out ...
Two-Stage, Pipelined Register Renaming

Register renaming is a performance-critical component of modern, dynamically-scheduled processors. Register renaming latency increases as a function of several architectural parameters (e.g., processor issue width, processor window size, and processor ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICS '92: Proceedings of the 6th international conference on Supercomputing

August 1992

495 pages

ISBN:0897914856

DOI:10.1145/143369

Chairmen:
Ken Kennedy
Rice University, Houston, TX
,
Constantine D. Polychronopoulos
Kubota Pacific Computers and CSRD

Copyright © 1992 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1992

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICS92

Sponsor:

SIGARCH

ICS92: ACM SIGARCH International Conference on Supercomputing

July 19 - 24, 1992

D. C., Washington, USA

Acceptance Rates

Overall Acceptance Rate 629 of 2,180 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

45
Total Citations
View Citations
390
Total Downloads

Downloads (Last 12 months)54
Downloads (Last 6 weeks)6

Reflects downloads up to 12 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Eichenberger ADavidson EAbraham S(2016)Minimizing Register Requirements of a Modulo Schedule via Optimum Stage SchedulingInternational Journal of Parallel Programming10.1007/BF0335674424:2(103-132)Online publication date: 26-May-2016
https://doi.org/10.1007/BF03356744
Eichenberger ADavidson EAbraham S(2014)Optimum modulo schedules for minimum register requirementsACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667171(227-236)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667171
Eichenberger ADavidson EAbraham S(2014)Author retrospective for optimum modulo schedules for minimum register requirementsACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2591653(35-36)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2591653
Huang YLi QXue C(2011)Minimizing Schedule Length via Cooperative Register Allocation and Loop Scheduling for Embedded SystemsProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.142(1038-1044)Online publication date: 16-Nov-2011
https://dl.acm.org/doi/10.1109/TrustCom.2011.142
Touati S(2007)On Periodic Register Need in Software PipeliningIEEE Transactions on Computers10.1109/TC.2007.7075256:11(1493-1504)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TC.2007.70752
Llosa JValero MFortes JAyguade E(2005)Using sacks to organize registers in VLIW machinesParallel Processing: CONPAR 94 — VAPP VI10.1007/3-540-58430-7_55(628-639)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-58430-7_55
Zalamea JLlosa JAyguadé EValero M(2004)Register Constrained Modulo SchedulingIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2004.127809915:5(417-430)Online publication date: 1-May-2004
https://dl.acm.org/doi/10.1109/TPDS.2004.1278099
Zalamea JLlosa JAyguadé EValero M(2003)MIRS: Modulo Scheduling with Integrated Register SpillingLanguages and Compilers for Parallel Computing10.1007/3-540-35767-X_16(239-253)Online publication date: 13-May-2003
https://doi.org/10.1007/3-540-35767-X_16
Wang ZSha EWang Y(2002)Partitioning and scheduling DSP applications with maximal memory access hidingEURASIP Journal on Advances in Signal Processing10.5555/1283100.12831942002:1(926-935)Online publication date: 1-Jan-2002
https://dl.acm.org/doi/10.5555/1283100.1283194
Zalamea JLlosa JAyguadé EValero M(2001)MIRSProceedings of the 14th international conference on Languages and compilers for parallel computing10.5555/1769331.1769347(239-253)Online publication date: 1-Aug-2001
https://dl.acm.org/doi/10.5555/1769331.1769347
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents