research-article

Design space exploration for field programmable compressor trees

Authors:

Seyed Hosein Attarzadeh Niaki,

Alessandro Cevrero,

Chrysostomos Nicopoulos,

Frank K. Gurkaynak,

Yusuf Leblebici,

Paolo IenneAuthors Info & Claims

CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems

Pages 207 - 216

https://doi.org/10.1145/1450095.1450126

Published: 19 October 2008 Publication History

Abstract

The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can be used to identify the best FPCT architecture for a given set of arithmetic benchmark circuits; in practice, an FPGA vendor can use the design space exploration to tailor the FPCT to meet the needs of the most important benchmark circuits of the vendor's largest-volume clients. One novel feature of the DSE is the introduction of a metric called I/O utilization; we found that I/O utilization has a strong correlation with both the critical path delay and area of the benchmark circuits under study. Pruning the search space using I/O utilization allowed us to reduce significantly the number of FPCTs that must be synthesized and evaluated during the DSE, while giving high confidence that the best architectures are still explored. The DSE was applied to seven small-to-medium range benchmark circuits; one FPCT architecture was found that was 30% faster than the second best in terms of critical path delay, and only 3.34% larger than the smallest.

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Cited By

Kamp WBainbridge-Smith AHayes M(2009)Efficient implementation of fast redundant number adders for long word-lengths in FPGAs2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377679(239-246)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377679

Index Terms

Design space exploration for field programmable compressor trees
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

cover image ACM Conferences

CASES '08: Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems

October 2008

274 pages

ISBN:9781605584690

DOI:10.1145/1450095

Program Chair:
Erik Altman
IBM

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 19 October 2008

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ESWEEK 08

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ESWEEK 08: Fourth Embedded Systems Week

October 19 - 24, 2008

GA, Atlanta, USA

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Cited By

Kamp WBainbridge-Smith AHayes M(2009)Efficient implementation of fast redundant number adders for long word-lengths in FPGAs2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377679(239-246)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377679

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