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Serial arithmetic techniques

Published: 30 November 1965 Publication History

Abstract

It has recently been suggested that the association of serial-mode functional (arithmetic) units with multi-instruction counter, multiprocessing computing systems may result in highly efficient processing complexes. This follows from the fact of life that in going from parallel to serial realizations of various algorithms the hardware requirements fall much more rapidly than does the speed. Furthermore the speeds of the slower, serial, arithmetic units may be more closely matched to those of memory and to other parts of the system. Thus the need for extra control circuitry, for high-speed registers, queueing circuits and look-ahead control, for example, is reduced and the system's overall cost/performance ratio improved. For appropriate serial configurations then, performance may be improved relative to a parallel system when system costs are to be held constant. Reconfiguration of a fast parallel circuit, for example, can yield a number of slower serial devices which, when kept busy, will increase throughput of the system.

References

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M. Lehman, "Serial Mode Operation and High Speed Parallel Processing," Information Processing 1965, Proceedings of IFIP Congress 65, part 2, New York (in press).
[2]
M. Lehman, "Serial Matrix Storage Systems," IRE Trans. on Electronic Computers, vol. EC-10, pp. 247--252 (June 1961).
[3]
K. Lonsdale and E. T. Warburton, "Mercury, A High-Speed Digital Computer," Proc. IEEE, suppl. no. 2 (Digital Computer Techniques), vol. 103, part B, pp. 174--183 (Apr. 1956).
[4]
M. Lehman, "A Comparative Study of Propagative Speed-Up Circuits in Binary Arithmetic Units," Information Processing 1962, Proceedings of IFIP Congress 62, North Holland Publishing Co., Amsterdam, 1963, pp. 671--677.
[5]
S. Winograd, "On the Time Required to Perform Addition," J. Assoc. Comp. Mach., vol. 12, no. 1, pp. 277--285 (Apr. 1965).
[6]
R. L. Ashenhurst and N. Metropolis, "Unnormalized Floating Point Arithmetic," J. Assoc. Comp. Mach.; vol. 6, no. 3, pp. 415--428 (July 1959).
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T. Kilburn et al, "Digital Computers at Manchester University," Proc. IEEE, part 2, vol. 100, pp. 487--500 (1953).
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A. W. Burkes, H. H. Goldstine and J. von Neuman, "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument," part 1, Institute of Advanced Study, Princeton, N. J., 1947.
[9]
D. J. Wheeler, "The Arithmetic Unit," University of Illinois, Digital Computer Laboratory, Report No. 92 (1959).
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E. Bloch, "The Central Processing Unit," Planning a Computer System, W. Bucholz, ed., McGraw-Hill, New York, 1962, chap. 14.
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C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. on Electronic Computers, vol. EC-13, pp. 14--17 (Feb. 1964).
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T. Lamdan, "Some Aspects of the Design of a Simultaneous Multiplier for a Parallel Binary Digital Computer," Ph.D. Thesis, University of Manchester, 1963.
[13]
M. Lehman, "Parallel Arithmetic Units and Their Control," Ph.D. Thesis, London University, Feb. 1957.
[14]
K. D. Tocher, "Techniques of Multiplication and Division for Automatic Binary Computers," Journ. Mech. Appl. Math., Aug. 1958, pp. 364--384.
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J. E. Robertson, "A New Class of Digital Division Methods," IRE Trans. on Electronic Computers, vol. EC-7, pp. 218--222 (Sept. 1958).
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C. V. Freiman, "Statistical Analysis of Certain Binary Division Techniques," Proc. IRE, vol. 49, no. 1, pp. 91--103 (Jan. 1961).
[17]
R. K. Richards, "Arithmetic Operations in Digital Computers," Van Nostrand, Princeton, N.J., 1955, pp. 279--282.

Cited By

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  • (2016)An efficient implementation of online arithmetic2016 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2016.7929191(69-76)Online publication date: Dec-2016
  • (1970)On Division by Functional IterationIEEE Transactions on Computers10.1109/T-C.1970.22301919:8(702-706)Online publication date: 1-Aug-1970
  • (1970)On Optimal Ierative Schemes for High-Speed DivisionIEEE Transactions on Computers10.1109/T-C.1970.22290119:3(227-231)Online publication date: 1-Mar-1970

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AFIPS '65 (Fall, part I): Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
November 1965
1119 pages
ISBN:9781450378857
DOI:10.1145/1463891
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 November 1965

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Cited By

View all
  • (2016)An efficient implementation of online arithmetic2016 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2016.7929191(69-76)Online publication date: Dec-2016
  • (1970)On Division by Functional IterationIEEE Transactions on Computers10.1109/T-C.1970.22301919:8(702-706)Online publication date: 1-Aug-1970
  • (1970)On Optimal Ierative Schemes for High-Speed DivisionIEEE Transactions on Computers10.1109/T-C.1970.22290119:3(227-231)Online publication date: 1-Mar-1970

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