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Fast instruction cache performance evaluation using compile-time analysis

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David B. WhalleyAuthors Info & Claims

ACM SIGMETRICS Performance Evaluation Review, Volume 20, Issue 1

Pages 13 - 22

https://doi.org/10.1145/149439.133081

Published: 01 June 1992 Publication History

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Cited By

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Schoeberl MBinder WVillazon A(2011)Design Space Exploration of Object Caches with Cross-ProfilingProceedings of the 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing10.1109/ISORC.2011.34(213-221)Online publication date: 28-Mar-2011
https://dl.acm.org/doi/10.1109/ISORC.2011.34
Sloane A(1997)Generating Dynamic Program Analysis ToolsProceedings of the Australian Software Engineering Conference10.5555/786774.787198Online publication date: 28-Sep-1997
https://dl.acm.org/doi/10.5555/786774.787198
Sloane A(1997)Generating dynamic program analysis toolsProceedings of Australian Software Engineering Conference ASWEC 9710.1109/ASWEC.1997.623768(166-173)Online publication date: 1997
https://doi.org/10.1109/ASWEC.1997.623768
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Fast instruction cache performance evaluation using compile-time analysis

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Fast instruction cache performance evaluation using compile-time analysis
SIGMETRICS '92/PERFORMANCE '92: Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Techniques for fast instruction cache performance evaluation
A Trace Cache Microarchitecture and Evaluation
Special issue on cache memory and related problems

As the instruction issue width of superscalar processors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional instruction caches hinder ...

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Published In

cover image ACM SIGMETRICS Performance Evaluation Review

ACM SIGMETRICS Performance Evaluation Review Volume 20, Issue 1

June 1992

260 pages

ISSN:0163-5999

DOI:10.1145/149439

Editor:
Blaine D. Gaither
Ahmdahl Corp., Rexburg, IN

Issue’s Table of Contents

SIGMETRICS '92/PERFORMANCE '92: Proceedings of the 1992 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
June 1992
267 pages
ISBN:0897915070
DOI:10.1145/133057
Chairman:
Michael K. Molloy
Hewlett Packard, Ft. Collins, CO
,
Editor:
Blaine D. Gaither
Amdahl Corp., Rexburg, ID

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1992

Published in SIGMETRICS Volume 20, Issue 1

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Cited By

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Schoeberl MBinder WVillazon A(2011)Design Space Exploration of Object Caches with Cross-ProfilingProceedings of the 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing10.1109/ISORC.2011.34(213-221)Online publication date: 28-Mar-2011
https://dl.acm.org/doi/10.1109/ISORC.2011.34
Sloane A(1997)Generating Dynamic Program Analysis ToolsProceedings of the Australian Software Engineering Conference10.5555/786774.787198Online publication date: 28-Sep-1997
https://dl.acm.org/doi/10.5555/786774.787198
Sloane A(1997)Generating dynamic program analysis toolsProceedings of Australian Software Engineering Conference ASWEC 9710.1109/ASWEC.1997.623768(166-173)Online publication date: 1997
https://doi.org/10.1109/ASWEC.1997.623768
Whalley D(1993)Techniques for fast instruction cache performance evaluationSoftware—Practice & Experience10.1002/spe.438023010723:1(95-118)Online publication date: 1-Jan-1993
https://dl.acm.org/doi/10.1002/spe.4380230107
Kroupis NSoudris D(2009)High-level estimation methodology for designing the instruction cache memory of programmable embedded platformsIET Computers & Digital Techniques10.1049/iet-cdt:200800093:2(205)Online publication date: 2009
https://doi.org/10.1049/iet-cdt:20080009
Kroupis NMamagkakis SSoudris D(2006)An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia10.1109/ESTMED.2006.321269(21-26)Online publication date: Oct-2006
https://doi.org/10.1109/ESTMED.2006.321269
Abraham SMahlke SRonen RFarrens MSpillinger I(1999)Automatic and efficient evaluation of memory hierarchies for embedded systemsProceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture10.5555/320080.320098(114-125)Online publication date: 16-Nov-1999
https://dl.acm.org/doi/10.5555/320080.320098
Abraham SMahlke S(1999)Automatic and efficient evaluation of memory hierarchies for embedded systemsMICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture10.1109/MICRO.1999.809449(114-125)Online publication date: 1999
https://doi.org/10.1109/MICRO.1999.809449
Conte TMenezes KMills PPatel B(1995)Optimization of instruction fetch mechanisms for high issue ratesACM SIGARCH Computer Architecture News10.1145/225830.22444423:2(333-344)Online publication date: 1-May-1995
https://dl.acm.org/doi/10.1145/225830.224444
Conte TMenezes KMills PPatel BPatterson D(1995)Optimization of instruction fetch mechanisms for high issue ratesProceedings of the 22nd annual international symposium on Computer architecture10.1145/223982.224444(333-344)Online publication date: 1-Jul-1995
https://dl.acm.org/doi/10.1145/223982.224444
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