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The implementation of the Cm* multi-microprocessor

Authors:

Richard J. Swan,

Andy Bechtolsheim,

Kwok-Woon Lai,

John K. OusterhoutAuthors Info & Claims

AFIPS '77: Proceedings of the June 13-16, 1977, national computer conference

Pages 645 - 655

https://doi.org/10.1145/1499402.1499516

Published: 13 June 1977 Publication History

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Abstract

The implementation of a hierarchical, packet switched multiprocessor is presented. The lowest level of the structure, a Computer Module, is a processor-memory pair. Computer Modules are grouped to form a cluster; communication within the cluster is via a parallel bus controlled by a centralized address mapping processor. Clusters communicate via intercluster busses. A memory reference by a program may be routed, transparently, to any memory in the system. This paper discusses the hardware used to implement the communication mechanism. The use of special diagnostic hardware and performance models is also discussed.

References

[1]

Swan, R. J., S. H. Fuller, and D. P. Siewiorek, "Cm*: a Modular, Multi-Microprocessor", AFIPS Conference Proceedings, Vol. 46, 1977 National Computer Conference.

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[2]

Bell, C. G. and A. Newell, Computer Structures: Readings and Examples, McGraw-Hill, New York, New York, 1971.

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[3]

Swan, R. J., L. Raskin and A. Bechtolsheim, "Deadlock Issues in the Design of the Linc", Internal Memo, Computer Science Dept., Carnegie-Mellon University, March 1976.

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[4]

Swan, R. J., S. H. Fuller, and D. P. Siewiorek, "The Structure and Architecture of Cm*: A Modular, Multi-Microprocessor", The Computer Sciences Department Research Review 1975--1976. Carnegie-Mellon University, December 1976.

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[5]

Brown, K. Q., "Simulation of a Cm* Cluster", Internal Memo, Computer Science Dept., Carnegie-Mellon University, May 1976.

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Noda HNakajima MDosaka KNakata KHigashida MYamamoto OMizumoto KTanizaki TGyohten TOkuno YKondo HShimazu YArimoto KSaito KShimizu T(2007)The Design and Implementation of the Massively Parallel Processor Based on the Matrix ArchitectureIEEE Journal of Solid-State Circuits10.1109/JSSC.2006.88654542:1(183-192)Online publication date: Jan-2007
https://doi.org/10.1109/JSSC.2006.886545
Hennessy JHeinrich MGupta A(1999)Cache-coherent distributed shared memory: perspectives on its development and future challengesProceedings of the IEEE10.1109/5.74786387:3(418-429)Online publication date: Mar-1999
https://doi.org/10.1109/5.747863
Siegel HNation WKruskal CNapolitano L(1989)Using the multistage cube network topology in parallel supercomputersProceedings of the IEEE10.1109/5.4883377:12(1932-1953)Online publication date: Jan-1989
https://doi.org/10.1109/5.48833
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AFIPS '77: Proceedings of the June 13-16, 1977, national computer conference

June 1977

1039 pages

ISBN:9781450379144

DOI:10.1145/1499402

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 13 June 1977

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Noda HNakajima MDosaka KNakata KHigashida MYamamoto OMizumoto KTanizaki TGyohten TOkuno YKondo HShimazu YArimoto KSaito KShimizu T(2007)The Design and Implementation of the Massively Parallel Processor Based on the Matrix ArchitectureIEEE Journal of Solid-State Circuits10.1109/JSSC.2006.88654542:1(183-192)Online publication date: Jan-2007
https://doi.org/10.1109/JSSC.2006.886545
Hennessy JHeinrich MGupta A(1999)Cache-coherent distributed shared memory: perspectives on its development and future challengesProceedings of the IEEE10.1109/5.74786387:3(418-429)Online publication date: Mar-1999
https://doi.org/10.1109/5.747863
Siegel HNation WKruskal CNapolitano L(1989)Using the multistage cube network topology in parallel supercomputersProceedings of the IEEE10.1109/5.4883377:12(1932-1953)Online publication date: Jan-1989
https://doi.org/10.1109/5.48833
Fleisch B(1987)Distributed shared memory in a loosely coupled distributed systemACM SIGCOMM Computer Communication Review10.1145/55483.5551617:5(317-327)Online publication date: 1-Aug-1987
https://dl.acm.org/doi/10.1145/55483.55516
Fleisch B(1987)Distributed shared memory in a loosely coupled distributed systemProceedings of the ACM workshop on Frontiers in computer communications technology10.1145/55482.55516(317-327)Online publication date: 1-Aug-1987
https://dl.acm.org/doi/10.1145/55482.55516
Siegel HSchwederski TMeyer DHsu T(1987)Large-scale parallel processing systemsMicroprocessors & Microsystems10.1016/0141-9331(87)90325-511:1(3-20)Online publication date: 1-Jan-1987
https://dl.acm.org/doi/10.1016/0141-9331%2887%2990325-5
Arvind Iannucci RLawson HAgerwala THeilborn HAiso HThorelli LBaer JTokoro M(1983)A critique of multiprocessing von Neumann styleProceedings of the 10th annual international symposium on Computer architecture10.1145/800046.801684(426-436)Online publication date: 13-Jun-1983
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Arvind Iannucci R(1983)A critique of multiprocessing von Neumann styleACM SIGARCH Computer Architecture News10.1145/1067651.80168411:3(426-436)Online publication date: 13-Jun-1983
https://dl.acm.org/doi/10.1145/1067651.801684
Egan R(1982)The effect of VLSI on computer architectureACM SIGARCH Computer Architecture News10.1145/641559.64156310:5(19-22)Online publication date: 1-Sep-1982
https://dl.acm.org/doi/10.1145/641559.641563
Grosser JTalukdar S(1982)Models for MIMD MachinesIEEE Transactions on Power Apparatus and Systems10.1109/TPAS.1982.317245PAS-101:1(94-99)Online publication date: Jan-1982
https://doi.org/10.1109/TPAS.1982.317245
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Cm*: a modular, multi-microprocessor

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Cm*: a modular, multi-microprocessor

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A general multi-microprocessor interconnection mechanism for non-numeric processing

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