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Complete information flow tracking from the gates up

Published: 07 March 2009 Publication History

Abstract

For many mission-critical tasks, tight guarantees on the flow of information are desirable, for example, when handling important cryptographic keys or sensitive financial data. We present a novel architecture capable of tracking all information flow within the machine, including all explicit data transfers and all implicit flows (those subtly devious flows caused by not performing conditional operations). While the problem is impossible to solve in the general case, we have created a machine that avoids the general-purpose programmability that leads to this impossibility result, yet is still programmable enough to handle a variety of critical operations such as public-key encryption and authentication. Through the application of our novel gate-level information flow tracking method, we show how all flows of information can be precisely tracked. From this foundation, we then describe how a class of architectures can be constructed, from the gates up, to completely capture all information flows and we measure the impact of doing so on the hardware implementation, the ISA, and the programmer.

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  • (2024)Hardware/software security co-verification and vulnerability detectionIntegration, the VLSI Journal10.1016/j.vlsi.2023.10208994:COnline publication date: 1-Jan-2024
  • (2023)SeVNoC: Security Validation of System-on-Chip Designs With NoC FabricsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317930742:2(672-682)Online publication date: Feb-2023
  • (2023)Anwendung II: SicherheitsvalidierungAutomatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme10.1007/978-3-031-36997-1_5(113-134)Online publication date: 20-Sep-2023
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  1. Complete information flow tracking from the gates up

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      Published In

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 44, Issue 3
      ASPLOS 2009
      March 2009
      346 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/1508284
      Issue’s Table of Contents
      • cover image ACM Conferences
        ASPLOS XIV: Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
        March 2009
        358 pages
        ISBN:9781605584065
        DOI:10.1145/1508244
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 07 March 2009
      Published in SIGPLAN Volume 44, Issue 3

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      Author Tags

      1. gate level
      2. information flow tracking
      3. provably sound

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      Cited By

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      • (2024)Hardware/software security co-verification and vulnerability detectionIntegration, the VLSI Journal10.1016/j.vlsi.2023.10208994:COnline publication date: 1-Jan-2024
      • (2023)SeVNoC: Security Validation of System-on-Chip Designs With NoC FabricsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317930742:2(672-682)Online publication date: Feb-2023
      • (2023)Anwendung II: SicherheitsvalidierungAutomatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme10.1007/978-3-031-36997-1_5(113-134)Online publication date: 20-Sep-2023
      • (2023)CAD for Information Leakage AssessmentCAD for Hardware Security10.1007/978-3-031-26896-0_4(81-102)Online publication date: 28-Jan-2023
      • (2022)A Gate-Level Information Leakage Detection Framework of Sequential Circuit Using Z3Electronics10.3390/electronics1124421611:24(4216)Online publication date: 16-Dec-2022
      • (2022)RTL-ConTest: Concolic Testing on RTL for Detecting Security VulnerabilitiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.306656041:3(466-477)Online publication date: Mar-2022
      • (2022)Isadora: automated information-flow property generation for hardware security verificationJournal of Cryptographic Engineering10.1007/s13389-022-00306-w13:4(391-407)Online publication date: 11-Nov-2022
      • (2021)Context-Aware Privacy-Optimizing Address Tracing2021 International Symposium on Secure and Private Execution Environment Design (SEED)10.1109/SEED51797.2021.00027(150-162)Online publication date: Sep-2021
      • (2021)Integrating Information Flow Tracking into High-Level Synthesis Design FlowBehavioral Synthesis for Hardware Security10.1007/978-3-030-78841-4_16(365-387)Online publication date: 28-May-2021
      • (2020)MITOS: Optimal Decisioning for the Indirect Flow Propagation Dilemma in Dynamic Information Flow Tracking Systems2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS)10.1109/ICDCS47774.2020.00093(1090-1100)Online publication date: Nov-2020
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