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Case study of finite resource optimization in FPGA using genetic algorithm

Authors:

JingXia Wang,

Sin Ming LooAuthors Info & Claims

GEC '09: Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation

Pages 989 - 992

https://doi.org/10.1145/1543834.1543990

Published: 12 June 2009 Publication History

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Abstract

Modern Field-Programmable Gate Arrays (FPGAs) are becoming very popular in embedded systems and high-performance applications. FPGA has benefited from the shrinking of transistor feature size, which allows more on-chip reconfigurable (e.g. memories and look-up tables) and routing resources. Unfortunately, the amount of reconfigurable resources in a FPGA is fixed and limited. This paper investigates an application-mapping scheme in FPGA by utilizing sequential processing units and task specific hardware. Genetic Algorithm is used in this study. We found that placing sequential processor cores into FPGA can improve the resource utilization efficiency and achieved acceptable system performance. In this paper, two cases were studied to determine the trade-off between resource optimization and system performance.

References

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Xilinx Virtex-II Pro and Virtex-II Pro X Platform FPGAs. http://direct.xilinx.com/bvdocs/publications/ds083.pdf

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Sin Ming Loo, Earl Wells. 2006. Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment. INFORMS Journal of Computing, Vol.18, No.2

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David Lee McCarver. 2005. Finite Resource Reconfigurable Hardware/Software Codesign: Case Studies, M.S. Dissertation in computer Engineering, Boise State University, USA.

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Theerayod WiangTong, Peter Y.K. Cheung, and Wayne Luk. 2002. Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Design Automation for Embedded Systems. pp. 425--449.

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Sumanth Donthi, and Roger L. Haggard. 2003. A Survey of Dynamically Reconfigurable FPGA Devices. Proceedings of the 35th Southeastern Symposium on System Theory, March 16--18, pp. 422--426.

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Cited By

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Kao C(2015)Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.231292426:3(858-867)Online publication date: Mar-2015
https://doi.org/10.1109/TPDS.2014.2312924
Huang MNarayana VBakhouya MGaber JEl-Ghazawi T(2012)Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural VariantsIEEE Transactions on Computers10.1109/TC.2011.15361:9(1354-1360)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1109/TC.2011.153
Fremal SBagein MManneback P(2012)Optimizing performance of batch of applications on cloud servers exploiting multiple GPUs2012 IEEE International Conference on Complex Systems (ICCS)10.1109/ICoCS.2012.6458590(1-6)Online publication date: Nov-2012
https://doi.org/10.1109/ICoCS.2012.6458590

Index Terms

Case study of finite resource optimization in FPGA using genetic algorithm
1. Computing methodologies
  1. Artificial intelligence
    1. Planning and scheduling
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

GEC '09: Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation

June 2009

1112 pages

ISBN:9781605583266

DOI:10.1145/1543834

General Chairs:
Lihong Xu
Tongji University, China
,
Erik D. Goodman
Michigan State University, USA
,
Program Chairs:
Guoliang Chen
University of Sci. & Tech. of China
,
Darrell Whitley
Colorado State University, USA
,
Yongsheng Ding
Donghua University, China

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Association for Computing Machinery

New York, NY, United States

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Published: 12 June 2009

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GEC '09: GEC '09 - ACM/SIGEVO Genetic and Evolutionary Computation Summit

June 12 - 14, 2009

Shanghai, China

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Kao C(2015)Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2014.231292426:3(858-867)Online publication date: Mar-2015
https://doi.org/10.1109/TPDS.2014.2312924
Huang MNarayana VBakhouya MGaber JEl-Ghazawi T(2012)Efficient Mapping of Task Graphs onto Reconfigurable Hardware Using Architectural VariantsIEEE Transactions on Computers10.1109/TC.2011.15361:9(1354-1360)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1109/TC.2011.153
Fremal SBagein MManneback P(2012)Optimizing performance of batch of applications on cloud servers exploiting multiple GPUs2012 IEEE International Conference on Complex Systems (ICCS)10.1109/ICoCS.2012.6458590(1-6)Online publication date: Nov-2012
https://doi.org/10.1109/ICoCS.2012.6458590

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A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems

Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine

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