Statistical static timing analysis considering leakage variability in power gated designs
Authors: 
Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek Sinkar, Nam Sung KimAuthors Info & Claims
Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek Sinkar, Nam Sung KimAuthors Info & ClaimsPages 57 - 62
Abstract
This paper is the first to study the impact of fluctuations in virtual power supply rail (vvdd) of power-gated designs on the circuit timing, where the vvdd fluctuations are due to process-induced leakage variability. We present a Monte Carlo-based statistical static timing analysis (SSTA) framework which accurately accounts for process-induced leakage variability and its impact on vvdd fluctuations and timing. For vvdd computation we propose an efficient and fast converging iterative analysis, which we explore to result in minimal additional complexity to traditional SSTA where leakage variability is not considered during analysis. We provide separate discussions for the two cases of SSTA for power-gated ASICs and microprocessors; in the latter we also consider process-induced dynamic power variability. In our simulations, we show significant error in traditional SSTA. We also study the impact of number of power-gated clusters on leakage variability, vvdd fluctuations and timing variations. We show that increase in the number of power-gated clusters reduces the circuit timing variance.
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Index Terms
- Statistical static timing analysis considering leakage variability in power gated designs
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Published In
August 2009
452 pages
ISBN:9781605586847
DOI:10.1145/1594233
- General Chairs:
- Jörg Henkel,
- Ali Keshavarzi,
- Program Chairs:
- Naehyuck Chang,
- Tahir Ghani
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Published: 19 August 2009
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ISLPED'09: International Symposium on Low Power Electronics and Design
August 19 - 21, 2009
CA, San Fancisco, USA
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ISLPED '09 Paper Acceptance Rate 72 of 208 submissions, 35%;
Overall Acceptance Rate 398 of 1,159 submissions, 34%
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