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Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation

Authors:

Marc Pouzet,

Pascal RaymondAuthors Info & Claims

EMSOFT '09: Proceedings of the seventh ACM international conference on Embedded software

Pages 215 - 224

https://doi.org/10.1145/1629335.1629365

Published: 12 October 2009 Publication History

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Abstract

This paper addresses the question of producing modular sequential imperative code from synchronous data-flow networks. Precisely, given a system with several input and output flows, how to decompose it into a minimal number of sub-systems executed atomically and statically scheduled without restricting possible feedback loops between input and output?

Though this question has been identified by Raymond in the early years of Lustre, it has almost been left aside until the recent work of Lublinerman, Szegedy and Tripakis. The problem is proven to be intractable, in the sense that it belongs to the family of optimization problems where the corresponding decision problem -- there exists a solution with size c -- is NP-complete. Then, the authors derive an iterative algorithm looking for solutions for c = 1, 2, ... where each step is encoded as a SAT problem.

Despite the apparent intractability of the problem, our experience is that real programs do not exhibit such a complexity. Based on earlier work by Raymond, this paper presents a new symbolic encoding of the problem in terms of input/output relations. This encoding simplifies the problem, in the sense that it rejects solutions, while keeping all the optimal ones. It allows, in polynomial time, (1) to identify nodes for which several schedules are feasible and thus are possible sources of combinational explosion; (2) to obtain solutions which in some cases are already optimal; (3) otherwise, to get a non trivial lower bound for c to start an iterative combinational search.

The solution applies to a large class of block-diagram formalisms based on atomic computations and a delay operator, ranging from synchronous languages such as Lustre or Scade to modeling tools such as Simulink.

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Colaco JPagano BPasteur CPouzet M(2018)Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore2018 Forum on Specification & Design Languages (FDL)10.1109/FDL.2018.8524052(5-16)Online publication date: Sep-2018
https://doi.org/10.1109/FDL.2018.8524052
Tripakis SLublinerman R(2018)Modular Code Generation from Synchronous Block Diagrams: Interfaces, Abstraction, CompositionalityPrinciples of Modeling10.1007/978-3-319-95246-8_26(449-477)Online publication date: 20-Jul-2018
https://doi.org/10.1007/978-3-319-95246-8_26
Bourke TBrun LDagand PLeroy XPouzet MRieg L(2017)A formally verified compiler for LustreACM SIGPLAN Notices10.1145/3140587.306235852:6(586-601)Online publication date: 14-Jun-2017
https://dl.acm.org/doi/10.1145/3140587.3062358
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Index Terms

Modular static scheduling of synchronous data-flow networks: an efficient symbolic representation
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language types
        Data flow languages

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Published In

EMSOFT '09: Proceedings of the seventh ACM international conference on Embedded software

October 2009

332 pages

ISBN:9781605586274

DOI:10.1145/1629335

Program Chairs:
Samarjit Chakraborty
TU Munich, Germany
,
Nicolas Halbwachs
Verimag/CNRS, Grenoble, France

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Publication History

Published: 12 October 2009

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ESWeek '09

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ESWeek '09: Fifth Embedded Systems Week

October 12 - 16, 2009

Grenoble, France

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EMSOFT '09 Paper Acceptance Rate 33 of 106 submissions, 31%;

Overall Acceptance Rate 60 of 203 submissions, 30%

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Cited By

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Colaco JPagano BPasteur CPouzet M(2018)Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore2018 Forum on Specification & Design Languages (FDL)10.1109/FDL.2018.8524052(5-16)Online publication date: Sep-2018
https://doi.org/10.1109/FDL.2018.8524052
Tripakis SLublinerman R(2018)Modular Code Generation from Synchronous Block Diagrams: Interfaces, Abstraction, CompositionalityPrinciples of Modeling10.1007/978-3-319-95246-8_26(449-477)Online publication date: 20-Jul-2018
https://doi.org/10.1007/978-3-319-95246-8_26
Bourke TBrun LDagand PLeroy XPouzet MRieg L(2017)A formally verified compiler for LustreACM SIGPLAN Notices10.1145/3140587.306235852:6(586-601)Online publication date: 14-Jun-2017
https://dl.acm.org/doi/10.1145/3140587.3062358
Bourke TBrun LDagand PLeroy XPouzet MRieg LCohen AVechev M(2017)A formally verified compiler for LustreProceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3062341.3062358(586-601)Online publication date: 14-Jun-2017
https://dl.acm.org/doi/10.1145/3062341.3062358
Beaugnon UCohen APouzet M(2016)In-Place Update in a Dataflow Synchronous LanguageProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems10.1145/2906363.2906379(40-49)Online publication date: 23-May-2016
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(2015)Towards refinement types for time-dependent data-flow networksProceedings of the 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2015.7340465(36-41)Online publication date: 1-Sep-2015
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Zhu QDeng PSze CDavoodi A(2014)Design synthesis and optimization for automotive embedded systemsProceedings of the 2014 on International symposium on physical design10.1145/2560519.2565873(141-148)Online publication date: 30-Mar-2014
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