Adding a new dimension to physical design

Three-dimensional (3D) technologies have the potential to provide major benefits to integrated circuit design. An advanced 3D chip consists of multiple tiers of two-dimensional (2D) circuitry, stacked vertically over each other, with very small intertier distances. Such technologies offer numerous benefits over conventional 2D designs. First, by stacking multiple 2D tiers, it is possible to increase the number of transistors within a package: in other words, 3D offers increased integration using an approach that is orthogonal to device scaling. Second, the small intertier distances imply that the histogram of wire length distributions is significantly altered, enabling critical wires to be made very short. Third, 3D offers opportunities for integrating heterogeneous technologies into a single chip, enabling much more versatility in the types of chips we can build.

Fundamentally, the shift from 2D to 3D is topological, and holds numerous physical design challenges. In addition, several effects that were critical in 2D are further accentuated in 3D. For example, the increased current required by a 3D stack, as compared to a 2D chip with the same footprint, brings forth twin problems: how do we get the current in (i.e., perform reliable power delivery), and how do we get the heat out (i.e., perform thermal management)? Solutions to problems such as these can come from the architectural level and go down to much finer granularities. This talk overviews prior work in the area, and surveys the challenges and opportunities ahead.