A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems

Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been proposed to address such issues but they all heavily depend on accurate knowledge of the chip's thermal state during runtime. In this paper we describe a unified statistical framework for designing an on-chip thermal sensing infrastructure which can be used to track the chip's thermal state at runtime. Specifically we address the following problems: (1)sensor placement; (2)sensor data compression; (3)sensor data fusion; (4)overall interplay. Our methods exploit the thermal correlation to generate the overall solution in both the noiseless and noisy sensor settings. Our framework is also capable of choosing the appropriate degree of compression for each sensor while accounting for their local space constraints when doing the sensor deployment. The experimental results showed that our infrastructure can improve the temperature estimation accuracy by 27% (on average) as compared to an equivalent system that uses range-based placement and uniform compression. It took our methods about 6.3 seconds to decide the overall solution for placement, compression and data fusion at design stage. This demonstrates the effectiveness and applicability of our unified statistical design methodology.