research-article

Shoestring: probabilistic soft error reliability on the cheap

Authors:

Shantanu Gupta,

Scott MahlkeAuthors Info & Claims

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems

Pages 385 - 396

https://doi.org/10.1145/1736020.1736063

Published: 13 March 2010 Publication History

Abstract

Aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in individual device reliability as transistors become increasingly susceptible to soft errors. We are quickly approaching a new era where resilience to soft errors is no longer a luxury that can be reserved for just processors in high-reliability, mission-critical domains. Even processors used in mainstream computing will soon require protection. However, due to tighter profit margins, reliable operation for these devices must come at little or no cost. This paper presents Shoestring, a minimally invasive software solution that provides high soft error coverage with very little overhead, enabling its deployment even in commodity processors with "shoestring" reliability budgets. Leveraging intelligent analysis at compile time, and exploiting low-cost, symptom-based error detection, Shoestring is able to focus its efforts on protecting statistically-vulnerable portions of program code. Shoestring effectively applies instruction duplication to protect only those segments of code that, when subjected to a soft error, are likely to result in user-visible faults without first exhibiting symptomatic behavior. Shoestring is able to recover from an additional 33.9% of soft errors that are undetected by a symptom-only approach, achieving an overall user-visible failure rate of 1.6%. This reliability improvement comes at a modest performance overhead of 15.8%.

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Index Terms

Shoestring: probabilistic soft error reliability on the cheap
1. Hardware
  1. Hardware test
  2. Robustness
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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cover image ACM Conferences

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems

March 2010

422 pages

ISBN:9781605588391

DOI:10.1145/1736020

General Chair:
James C. Hoe
Carnegie Mellon University, USA
,
Program Chair:
Vikram S. Adve
University of Illinois at Urbana-Champaign, USA

ACM SIGARCH Computer Architecture News Volume 38, Issue 1
ASPLOS '10
March 2010
399 pages
ISSN:0163-5964
DOI:10.1145/1735970
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 45, Issue 3
ASPLOS '10
March 2010
399 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1735971
Issue’s Table of Contents

Copyright © 2010 ACM.

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Published: 13 March 2010

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ASPLOS '10: Architectural Support for Programming Languages and Operating Systems

March 13 - 17, 2010

Pennsylvania, Pittsburgh, USA

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ASPLOS XV Paper Acceptance Rate 32 of 181 submissions, 18%;

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Cited By

Ratti FKnödtel JReichenbach M(2025)HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing CostACM Transactions on Embedded Computing Systems10.1145/371206224:2(1-50)Online publication date: 17-Jan-2025
https://dl.acm.org/doi/10.1145/3712062
Liao MAinsworth SMukhanov LJones TKluss DAchour SPalsberg J(2025)A Deep Technical Review of nZDC Fault ToleranceProceedings of the 34th ACM SIGPLAN International Conference on Compiler Construction10.1145/3708493.3712688(104-116)Online publication date: 25-Feb-2025
https://dl.acm.org/doi/10.1145/3708493.3712688
Joshi KSingh RBassetto TAdve SMarinov DMisailovic SDoerfert JGrosser TLeather HSadayappan P(2025)FastFlip: Compositional SDC Resiliency AnalysisProceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization10.1145/3696443.3708938(362-376)Online publication date: 1-Mar-2025
https://dl.acm.org/doi/10.1145/3696443.3708938
Baroffio DReghenzani FFornaciari W(2024)Enhanced Compiler Technology for Software-based Hardware Fault DetectionACM Transactions on Design Automation of Electronic Systems10.1145/366052429:5(1-23)Online publication date: 22-Apr-2024
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Rogenmoser MTortorella YRossi DConti FBenini L(2023)Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-core Computing Clusters for Reliable Processing in SpaceACM Transactions on Cyber-Physical Systems10.1145/36351619:1(1-29)Online publication date: 30-Nov-2023
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He ZHuang YXu HTao DLi GMohror KArnold DBadia R(2023)Demystifying and Mitigating Cross-Layer Deficiencies of Soft Error Protection in Instruction DuplicationProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3581784.3607078(1-13)Online publication date: 12-Nov-2023
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Sangchoolie BPattabiraman KKarlsson J(2022)An Empirical Study of the Impact of Single and Multiple Bit-Flip Errors in ProgramsIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2020.304302319:3(1988-2006)Online publication date: 1-May-2022
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