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High performance parallel logic simulations on a network of workstations

Published: 01 July 1993 Publication History

Abstract

An approach for high performance parallel logic simulation on a local area network of workstation computers is discussed in this paper. The single, shared transmission medium often found in such networks places limitations on parallel execution, hence a reduction in the frequency of synchronization is pursued by combining a circuit partitioning methodology with a specific synchronization constraint. A consequence of the partitioning methodology is replication of objects between blocks of a partition. A partitioning procedure based on iterative improvement is described for reducing replication while preserving load balance. Two interprocessor synchronization techniques for parallel simulation are studied: conservative and optimistic synchronization. Experiments conducted on three large sequential circuits indicate that reasonable speedup is achievable for well-balanced partitions, and that optimistic synchronization provides a modest improvement in performance over conservative synchronization.

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Published In

cover image ACM SIGSIM Simulation Digest
ACM SIGSIM Simulation Digest  Volume 23, Issue 1
July 1993
164 pages
ISSN:0163-6103
DOI:10.1145/174134
Issue’s Table of Contents
  • cover image ACM Conferences
    PADS '93: Proceedings of the seventh workshop on Parallel and distributed simulation
    July 1993
    168 pages
    ISBN:1565550552
    DOI:10.1145/158459

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993
Published in SIGSIM Volume 23, Issue 1

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