poster

Energy-efficient redundant execution for chip multiprocessors

Authors:

Pramod Subramanyan,

Virendra Singh,

Kewal K. Saluja,

Erik LarssonAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 143 - 146

https://doi.org/10.1145/1785481.1785516

Published: 16 May 2010 Publication History

Abstract

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

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P. Subramanyan, V. Singh, K. K. Saluja, and E. Larsson. Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding. To appear in Proc. of DSN, 2010.

Cited By

Venkatesha SParthasarathi R(2019)32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Â„Tolerant Core for Multicore SystemsJournal of Testing and Evaluation10.1520/JTE2018049247:6(20180492)Online publication date: 31-Jan-2019
https://doi.org/10.1520/JTE20180492
Oz IArslan S(2019)A Survey on Multithreading Alternatives for Soft Error Fault ToleranceACM Computing Surveys10.1145/330225552:2(1-38)Online publication date: 27-Mar-2019
https://dl.acm.org/doi/10.1145/3302255
Gopalakrishnan SSingh V(2019)Soft‐error reliable architecture for future microprocessorsIET Computers & Digital Techniques10.1049/iet-cdt.2018.501513:3(233-242)Online publication date: 5-Mar-2019
https://doi.org/10.1049/iet-cdt.2018.5015
Show More Cited By

Index Terms

Energy-efficient redundant execution for chip multiprocessors
1. Computer systems organization
  1. Architectures

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Published In

cover image ACM Conferences

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 16 May 2010

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GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

Rhode Island, Providence, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Venkatesha SParthasarathi R(2019)32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Â„Tolerant Core for Multicore SystemsJournal of Testing and Evaluation10.1520/JTE2018049247:6(20180492)Online publication date: 31-Jan-2019
https://doi.org/10.1520/JTE20180492
Oz IArslan S(2019)A Survey on Multithreading Alternatives for Soft Error Fault ToleranceACM Computing Surveys10.1145/330225552:2(1-38)Online publication date: 27-Mar-2019
https://dl.acm.org/doi/10.1145/3302255
Gopalakrishnan SSingh V(2019)Soft‐error reliable architecture for future microprocessorsIET Computers & Digital Techniques10.1049/iet-cdt.2018.501513:3(233-242)Online publication date: 5-Mar-2019
https://doi.org/10.1049/iet-cdt.2018.5015
Subramanyan PSingh VSaluja KLarsson E(2011)Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessorsProceedings of the 2011 IEEE 29th International Conference on Computer Design10.1109/ICCD.2011.6081432(419-426)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1109/ICCD.2011.6081432
Subramanyan PSingh VSaluja KLarsson E(2010)Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN)10.1109/DSN.2010.5544918(121-130)Online publication date: Jun-2010
https://doi.org/10.1109/DSN.2010.5544918

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