research-article

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

Authors:

Harika Manem,

Garrett S. Rose,

Xiaoli He,

Wei WangAuthors Info & Claims

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

Pages 287 - 292

https://doi.org/10.1145/1785481.1785548

Published: 16 May 2010 Publication History

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Abstract

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

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Zhou XYu DLi ZYu SJunaid M(2023)A pulse train controlled Buck converter based on a single memristive multi-vibratorInternational Journal of Electronics10.1080/00207217.2023.2267211(1-23)Online publication date: 17-Oct-2023
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Index Terms

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
1. Hardware

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Published In

GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI

May 2010

502 pages

ISBN:9781450300124

DOI:10.1145/1785481

General Chairs:
R. Iris Bahar
Brown University, USA
,
Fabrizio Lombardi
Northeastern University, USA
,
Program Chairs:
David Atienza
EPFL, Switzerland
,
Erik Brunvand
University of Utah, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 16 May 2010

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GLSVLSI '10: Great Lakes Symposium on VLSI 2010

May 16 - 18, 2010

Rhode Island, Providence, USA

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Cited By

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https://doi.org/10.1109/TCAD.2022.3168782
Zhou XYu DLi ZYu SJunaid M(2023)A pulse train controlled Buck converter based on a single memristive multi-vibratorInternational Journal of Electronics10.1080/00207217.2023.2267211(1-23)Online publication date: 17-Oct-2023
https://doi.org/10.1080/00207217.2023.2267211
Sadi MSumon MAli M(2023)Soft Error Tolerant Memristor-Based MemoryProceedings of International Conference on Information and Communication Technology for Development10.1007/978-981-19-7528-8_33(421-434)Online publication date: 26-Jan-2023
https://doi.org/10.1007/978-981-19-7528-8_33
Wang SYuan GMa XLi YLin XKailkhura B(2022)Fault-Tolerant Deep Neural Networks for Processing-In-Memory based Autonomous Edge Systems2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774523(424-429)Online publication date: 14-Mar-2022
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Mohajeri NEbrahimi BDousti M(2021)HPM: High-Precision Modeling of a Low-Power Inverter-Based Memristive Neural NetworkJournal of Circuits, Systems and Computers10.1142/S021812662150274130:15Online publication date: 26-May-2021
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