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On testing cache-coherent shared memories

Authors:

Phillip B. Gibbons,

Ephraim KorachAuthors Info & Claims

SPAA '94: Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures

Pages 177 - 188

https://doi.org/10.1145/181014.181328

Published: 01 August 1994 Publication History

Abstract

Sequential consistency is the most-widely used correctness condition for multiprocessor memory systems. High-performance shared memory multiprocessors such as the Kendall Square KSR1, the Stanford DASH, and the MIT Alewife employ a variety of techniques to improve memory system performance while providing sequential consistency. Primary among them is the use of caches at each processor, kept coherent by protocols implemented in hardware.

We study the problem of testing shared memory multiprocessors to determine if they are indeed providing a sequentially consistent memory. We present a series of results for testing an execution of a shared memory under scenarios that exploit the cache-coherence protocol. In addition to reads and writes to the shared memory, we consider the more powerful read-modify-write, load-reserved, and store-conditional operations available in many cache-coherent multiprocessors.

Finally, we consider linearizability, another well-known correctness condition for shared memories. Linearizability imposes additional restrictions on the shared memory, beyond that of sequential consistency; we show that these restrictions are useful in testing such memories.

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Cited By

Chakraborty SKrishna SMathur UPavlogiannis A(2024)How Hard Is Weak-Memory Testing?Proceedings of the ACM on Programming Languages10.1145/36329088:POPL(1978-2009)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632908
Farzan AMathur U(2024)Coarser Equivalences for Causal ConcurrencyProceedings of the ACM on Programming Languages10.1145/36328738:POPL(911-941)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632873
Naylor MMoore SMujumdar APiskac RTalupur M(2016)A consistency checker for memory subsystem tracesProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077654(133-140)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.5555/3077629.3077654
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Index Terms

On testing cache-coherent shared memories
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Software defect analysis
        Software testing and debugging

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Published In

cover image ACM Conferences

SPAA '94: Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures

August 1994

374 pages

ISBN:0897916719

DOI:10.1145/181014

Chairmen:
Lawrence Snyder
Univ. of Washington, Seattle
,
Charles E. Leiserson
Massachusetts Institute of Technology, Cambridge

Copyright © 1994 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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European Comp Soc: European Computer Society
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1994

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6SPAA94

Sponsor:

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6SPAA94: 6th Annual ACM Symposium on Parallel Algorithms and Architectures

June 27 - 29, 1994

New Jersey, Cape May, USA

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Overall Acceptance Rate 447 of 1,461 submissions, 31%

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Cited By

Chakraborty SKrishna SMathur UPavlogiannis A(2024)How Hard Is Weak-Memory Testing?Proceedings of the ACM on Programming Languages10.1145/36329088:POPL(1978-2009)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632908
Farzan AMathur U(2024)Coarser Equivalences for Causal ConcurrencyProceedings of the ACM on Programming Languages10.1145/36328738:POPL(911-941)Online publication date: 5-Jan-2024
https://dl.acm.org/doi/10.1145/3632873
Naylor MMoore SMujumdar APiskac RTalupur M(2016)A consistency checker for memory subsystem tracesProceedings of the 16th Conference on Formal Methods in Computer-Aided Design10.5555/3077629.3077654(133-140)Online publication date: 3-Oct-2016
https://dl.acm.org/doi/10.5555/3077629.3077654
Naylor MMoore SMujumdar A(2016)A consistency checker for memory subsystem traces2016 Formal Methods in Computer-Aided Design (FMCAD)10.1109/FMCAD.2016.7886671(133-140)Online publication date: Oct-2016
https://doi.org/10.1109/FMCAD.2016.7886671
Lv YSun LYe XFan DWu P(2014)Efficiently and Completely Verifying Synchronized Consistency ModelsAutomated Technology for Verification and Analysis10.1007/978-3-319-11936-6_20(264-280)Online publication date: 2014
https://doi.org/10.1007/978-3-319-11936-6_20
Chen YChen TLi LWu RLiu DHu W(2013)Deterministic Replay Using Global ClockACM Transactions on Architecture and Code Optimization10.1145/2445572.244557310:1(1-28)Online publication date: 1-Apr-2013
https://dl.acm.org/doi/10.1145/2445572.2445573
Chen YLi LChen TLi LWang LFeng XHu W(2012)Program Regularization in Memory Consistency VerificationIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2012.4423:11(2163-2174)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TPDS.2012.44
Hu WChen YChen TQian CLi L(2012)Linear Time Memory Consistency VerificationIEEE Transactions on Computers10.1109/TC.2011.4161:4(502-516)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1109/TC.2011.41
Li LChen TChen YLi LQian CHu WMeyer auf der Heide FRajaraman R(2011)Brief announcementProceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures10.1145/1989493.1989535(265-266)Online publication date: 4-Jun-2011
https://dl.acm.org/doi/10.1145/1989493.1989535
Chen YHu WChen TWu R(2010)LReplayACM SIGARCH Computer Architecture News10.1145/1816038.181598538:3(187-197)Online publication date: 19-Jun-2010
https://dl.acm.org/doi/10.1145/1816038.1815985
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