research-article

Bridging pre-silicon verification and post-silicon validation

Authors:

Avi Ziv,

Alan Hu,

Shakti KapoorAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 94 - 95

https://doi.org/10.1145/1837274.1837300

Published: 13 June 2010 Publication History

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Abstract

Post-silicon validation is a necessary step in a design's verification process. Pre-silicon techniques such as simulation and emulation are limited in scope and volume as compared to what can be achieved on the silicon itself. Some parts of the verification, such as full-system functional verification, cannot be practically covered with current pre-silicon technologies. This panel brings together experts from industry, academia, and EDA to review the differences and similarities between pre- and post-silicon, discuss how the fundamental aspects of verification are affected by these differences, and explore how the gaps between the two worlds can be bridged.

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Mishra VMittal SMishra NSinghal R(2024)Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00091(511-516)Online publication date: 6-Jan-2024
https://doi.org/10.1109/VLSID60093.2024.00091
Sandru EDavid EKovacs IBuzo ABurileanu CPelz G(2022)Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield PredictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305480441:1(129-142)Online publication date: Jan-2022
https://doi.org/10.1109/TCAD.2021.3054804
Stuckmann FFistanto PPaya-Vaya G(2021)PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST52088.2021.9493373(1-6)Online publication date: 5-Jul-2021
https://doi.org/10.1109/MOCAST52088.2021.9493373
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Index Terms

Bridging pre-silicon verification and post-silicon validation
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Information

Published In

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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DAC '10

Sponsor:

EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

View all

Mishra VMittal SMishra NSinghal R(2024)Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00091(511-516)Online publication date: 6-Jan-2024
https://doi.org/10.1109/VLSID60093.2024.00091
Sandru EDavid EKovacs IBuzo ABurileanu CPelz G(2022)Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield PredictionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305480441:1(129-142)Online publication date: Jan-2022
https://doi.org/10.1109/TCAD.2021.3054804
Stuckmann FFistanto PPaya-Vaya G(2021)PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST52088.2021.9493373(1-6)Online publication date: 5-Jul-2021
https://doi.org/10.1109/MOCAST52088.2021.9493373
Beigmohammadi SAlizadeh B(2020)Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon DebugIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288396939:1(272-276)Online publication date: Jan-2020
https://doi.org/10.1109/TCAD.2018.2883969
Kovacs ITopa MPop CSandru EBuzo APelz G(2020)Correlating electrical and process parameters for yield detractors’ detection2020 International Symposium on Electronics and Telecommunications (ISETC)10.1109/ISETC50328.2020.9301121(1-4)Online publication date: 5-Nov-2020
https://doi.org/10.1109/ISETC50328.2020.9301121
Jindal NPanda PSarangi S(2018)Reusing Trace Buffers as Victim CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.282792826:9(1699-1712)Online publication date: Sep-2018
https://doi.org/10.1109/TVLSI.2018.2827928
Cheng YLi HWang YShen HLiu BLi X(2018)On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon DebugIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.277808437:10(2166-2179)Online publication date: 1-Oct-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2778084
Basu K(2018)Structural Signal Selection for Post-Silicon ValidationPost-Silicon Validation and Debug10.1007/978-3-319-98116-1_3(33-56)Online publication date: 2-Sep-2018
https://doi.org/10.1007/978-3-319-98116-1_3
Cong KXie F(2018)Coverage Evaluation and Analysis of Post-Silicon Tests with Virtual PrototypesPost-Silicon Validation and Debug10.1007/978-3-319-98116-1_14(275-306)Online publication date: 2-Sep-2018
https://doi.org/10.1007/978-3-319-98116-1_14
Rahmani KRay SMishra P(2017)Postsilicon Trace Signal Selection Using Machine Learning TechniquesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.259390225:2(570-580)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2593902
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Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

Post-silicon validation challenges: how EDA and academia can help

A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips