research-article

Pulsed-latch aware placement for timing-integrity optimization

Authors:

Yao-Wen ChangAuthors Info & Claims

DAC '10: Proceedings of the 47th Design Automation Conference

Pages 280 - 285

https://doi.org/10.1145/1837274.1837346

Published: 13 June 2010 Publication History

Abstract

Utilizing pulsed latches in a circuit is one emerging solution to timing improvements. Pulsed latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If pulse generators and pulsed latches are not placed properly, however, pulse-width degradations at pulsed latches and thus timing violations might occur. In this paper, we introduce the pulsed-latch aware placement problem for timing integrity and present a unified placement framework to tackle this problem. Our new placer has the following distinguished features: (1) a multilevel pulsed-latch aware analytical placement framework to effectively prevent the potential pulse-width distortion problem, (2) a physical-information aware latch grouping algorithm to identify each desired group of a pulse generator and pulsed latches, and (3) a new optimization gradient for global placement to consider the impact of load capacitance of generators. Experimental results show that our placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows.

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Cited By

Kumar KDhandapani V(2021)Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch CircuitAdvances in Energy Technology10.1007/978-981-16-1476-7_12(123-130)Online publication date: 28-Jul-2021
https://doi.org/10.1007/978-981-16-1476-7_12
Jin WKim SHe WMao ZSeok M(2017)Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design TechniquesIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.271792752:9(2475-2487)Online publication date: Sep-2017
https://doi.org/10.1109/JSSC.2017.2717927
Ding YJin WHe GHe W(2017)Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252643(985-988)Online publication date: Oct-2017
https://doi.org/10.1109/ASICON.2017.8252643
Show More Cited By

Index Terms

Pulsed-latch aware placement for timing-integrity optimization
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Conferences

DAC '10: Proceedings of the 47th Design Automation Conference

June 2010

1036 pages

ISBN:9781450300025

DOI:10.1145/1837274

General Chair:
Sachin Sapatnekar
Univ. of Minnesota, Minneapolis, MN

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2010

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National Science Council Taiwan

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DAC '10

Sponsor:

EDAC
SIGDA

DAC '10: The 47th Annual Design Automation Conference 2010

June 13 - 18, 2010

California, Anaheim

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Citations

Cited By

Kumar KDhandapani V(2021)Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch CircuitAdvances in Energy Technology10.1007/978-981-16-1476-7_12(123-130)Online publication date: 28-Jul-2021
https://doi.org/10.1007/978-981-16-1476-7_12
Jin WKim SHe WMao ZSeok M(2017)Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design TechniquesIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.271792752:9(2475-2487)Online publication date: Sep-2017
https://doi.org/10.1109/JSSC.2017.2717927
Ding YJin WHe GHe W(2017)Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252643(985-988)Online publication date: Oct-2017
https://doi.org/10.1109/ASICON.2017.8252643
Lin MChih-Cheng Hsu Yu-Chuan Chen (2015)Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.237698834:2(280-292)Online publication date: Feb-2015
https://doi.org/10.1109/TCAD.2014.2376988
Lin HChuang YYang ZHo T(2014)Pulsed-Latch Utilization for Clock-Tree Power OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225221122:4(721-733)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2252211
Hsu CChen YLin MHenkel J(2013)In-placement clock-tree aware multi-bit flip-flop generation for power optimizationProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561946(592-598)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561946
Chang CJiang I(2013)Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock GatingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.223482832:2(242-246)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TCAD.2012.2234828
Hsu CChen YLin M(2013)In-placement clock-tree aware multi-bit flip-flop generation for power optimization2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2013.6691177(592-598)Online publication date: Nov-2013
https://doi.org/10.1109/ICCAD.2013.6691177
Sangmin Kim Duckhwan Kim Youngsoo Shin (2013)Pulsed-latch ASIC synthesis in industrial design flow2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509621(356-361)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509621
Chang CJiang IYang YTsai EChen AHu JKoh C(2012)Novel pulsed-latch replacement based on time borrowing and spiral clusteringProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160944(121-128)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160944
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