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A holistic approach for statistical SRAM analysis

Published: 13 June 2010 Publication History

Abstract

We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives based on global corners or critical path netlist, which can lead to unexpected yield loss.

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Y. Zhou et al. "The impact of beol lithography effects on the sram cell performance and yield" Proc. ISQED, 2009, pp. 607--612.
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P. Zuber et al. "Statistical Memory Analysis for Yield Enhancement", Proc. DATE, 2010
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Cited By

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  • (2023)High Efficiency Variation-Aware SRAM Timing Characterization via Machine Learning-Assisted Netlist ExtractionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.3318577(1-1)Online publication date: 2023
  • (2013)Technique for Efficient Evaluation of SRAM Timing FailureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.221225421:8(1558-1562)Online publication date: 1-Aug-2013
  • (2012)Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash ArraysIEEE Electron Device Letters10.1109/LED.2011.217609933:2(164-166)Online publication date: Feb-2012
  • Show More Cited By

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Published In

cover image ACM Conferences
DAC '10: Proceedings of the 47th Design Automation Conference
June 2010
1036 pages
ISBN:9781450300025
DOI:10.1145/1837274
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 June 2010

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Author Tags

  1. process variability
  2. statistical SRAM analysis
  3. yield prediction

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Cited By

View all
  • (2023)High Efficiency Variation-Aware SRAM Timing Characterization via Machine Learning-Assisted Netlist ExtractionIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.3318577(1-1)Online publication date: 2023
  • (2013)Technique for Efficient Evaluation of SRAM Timing FailureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.221225421:8(1558-1562)Online publication date: 1-Aug-2013
  • (2012)Induced Variability of Cell-to-Cell Interference by Line Edge Roughness in nand Flash ArraysIEEE Electron Device Letters10.1109/LED.2011.217609933:2(164-166)Online publication date: Feb-2012
  • (2012)High-Sigma Verification and DesignVariation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide10.1007/978-1-4614-2269-3_5(115-167)Online publication date: 26-Sep-2012
  • (2011)Variability aware modeling for yield enhancement of SRAM and logic2011 Design, Automation & Test in Europe10.1109/DATE.2011.5763193(1-6)Online publication date: Mar-2011

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