research-article

Low power branch prediction for embedded application processors

Authors:

Shlomo WeissAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 67 - 72

https://doi.org/10.1145/1840845.1840860

Published: 18 August 2010 Publication History

Abstract

Modern embedded processors used in media and communication portable devices are now required to execute complex applications and their performance requirements are getting close to the demands of general purpose processors. The performance-per-Watt ratio is an extremely important measure in portable devices because of their limited power capacity. Branch predictors, and especially the BTB, are among the largest on-chip SRAM structures (after caches), and therefore are primary contributors to the total system power. We propose a novel micro-architectural method referred to as Shifted-Index BTB with a Set-Buffer, which reduces both dynamic and static power. Extensive simulations show that up to 80% reduction in dynamic power is achieved at the cost of up to 0.64% system slowdown. 58% reduction is static power is also achieved by applying low-leakage power techniques that mesh well with the Set-Buffer design.

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Cited By

Nian JLiu HGao XZhang SYang M(2024)Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction MechanismElectronics10.3390/electronics1307118513:7(1185)Online publication date: 23-Mar-2024
https://doi.org/10.3390/electronics13071185
Zhou CHuang LZhang TWang YZhang CDou Q(2017)Effective Optimization of Branch Predictors through Lightweight Simulation2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.114(653-656)Online publication date: Nov-2017
https://doi.org/10.1109/ICCD.2017.114
Kim NCho HEun CJeong O(2015)Performance improvement using two level branch predictor on the mobile processor2015 IEEE International Conference on Consumer Electronics - Taiwan10.1109/ICCE-TW.2015.7217014(49-50)Online publication date: Jun-2015
https://doi.org/10.1109/ICCE-TW.2015.7217014
Show More Cited By

Index Terms

Low power branch prediction for embedded application processors
1. General and reference
  1. Cross-computing tools and techniques
    1. Design

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Information

Published In

cover image ACM Conferences

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 August 2010

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ISLPED'10

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SIGDA

ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Nian JLiu HGao XZhang SYang M(2024)Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction MechanismElectronics10.3390/electronics1307118513:7(1185)Online publication date: 23-Mar-2024
https://doi.org/10.3390/electronics13071185
Zhou CHuang LZhang TWang YZhang CDou Q(2017)Effective Optimization of Branch Predictors through Lightweight Simulation2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.114(653-656)Online publication date: Nov-2017
https://doi.org/10.1109/ICCD.2017.114
Kim NCho HEun CJeong O(2015)Performance improvement using two level branch predictor on the mobile processor2015 IEEE International Conference on Consumer Electronics - Taiwan10.1109/ICCE-TW.2015.7217014(49-50)Online publication date: Jun-2015
https://doi.org/10.1109/ICCE-TW.2015.7217014
Bournoutian GOrailoglu A(2015)Mobile ecosystem driven application-specific low-power control microarchitectureProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357186(720-727)Online publication date: 18-Oct-2015
https://dl.acm.org/doi/10.1109/ICCD.2015.7357186
Peng MLiu X(2013)Adaptive Rapid Reconfigurable Algorithm for Low Power CacheProceedings of the 2013 International Conference on Computational and Information Sciences10.1109/ICCIS.2013.61(203-206)Online publication date: 21-Jun-2013
https://dl.acm.org/doi/10.1109/ICCIS.2013.61

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