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Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help

Authors:

Sandya S. Mannarswamy,

R. GovindarajanAuthors Info & Claims

PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques

Pages 547 - 548

https://doi.org/10.1145/1854273.1854345

Published: 11 September 2010 Publication History

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Abstract

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.

References

[1]

}}C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC '08, pages 35--46, Sep 2008.

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[2]

}}Larus J., Rajwar R. Transactional Memory. Morgan and Claypool Publishers.

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[3]

}}D. Dice, O. Shalev N. Shavit. Transactional locking II. DISC 2004

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Index Terms

Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help
1. Computing methodologies
  1. Concurrent computing methodologies
    1. Concurrent programming languages
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language types
        Concurrent programming languages

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Published In

PACT '10: Proceedings of the 19th international conference on Parallel architectures and compilation techniques

September 2010

596 pages

ISBN:9781450301787

DOI:10.1145/1854273

General Chair:
Valentina Salapura
IBM TJ Watson Research Center
,
Program Chairs:
Michael Gschwind
IBM Systems & Technology Group
,
Jens Knoop
Technische Universität Wien

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2010

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PACT '10

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IFIP WG 10.3
IEEE CS TCPP
SIGARCH
IEEE CS TCAA

PACT '10: International Conference on Parallel Architectures and Compilation Techniques

September 11 - 15, 2010

Vienna, Austria

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Overall Acceptance Rate 121 of 471 submissions, 26%

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