research-article

MPI as a Programming Model for High-Performance Reconfigurable Computers

Authors:

Manuel Saldaña,

Christopher Madill,

Andrew PutnamAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 3, Issue 4

Article No.: 22, Pages 1 - 29

https://doi.org/10.1145/1862648.1862652

Published: 01 November 2010 Publication History

Abstract

High-Performance Reconfigurable Computers (HPRCs) consist of one or more standard microprocessors tightly-coupled with one or more reconfigurable FPGAs. HPRCs have been shown to provide good speedups and good cost/performance ratios, but not necessarily ease of use, leading to a slow acceptance of this technology. HPRCs introduce new design challenges, such as the lack of portability across platforms, incompatibilities with legacy code, users reluctant to change their code base, a prolonged learning curve, and the need for a system-level Hardware/Software co-design development flow. This article presents the evolution and current work on TMD-MPI, which started as an MPI-based programming model for Multiprocessor Systems-on-Chip implemented in FPGAs, and has now evolved to include multiple X86 processors. TMD-MPI is shown to address current design challenges in HPRC usage, suggesting that the MPI standard has enough syntax and semantics to program these new types of parallel architectures. Also presented is the TMD-MPI Ecosystem, which consists of research projects and tools that are developed around TMD-MPI to further improve HPRC usability. Finally, we present preliminary communication performance measurements.

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Arthanto YOjika DKim J(2022)FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00042(218-224)Online publication date: Aug-2022
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MPI as a Programming Model for High-Performance Reconfigurable Computers

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 3, Issue 4

November 2010

240 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1862648

Issue’s Table of Contents

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 November 2010

Accepted: 01 August 2009

Revised: 01 June 2009

Received: 01 March 2009

Published in TRETS Volume 3, Issue 4

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https://doi.org/10.1109/ICFPT51103.2020.00030
Haghi PGuo AXiong QPatel RYang CGeng TBroaddus JMarshall RSkjellum AHerbordt M(2020)FPGAs in the Network and Novel Communicator Support Accelerate MPI Collectives2020 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC43674.2020.9286200(1-10)Online publication date: 22-Sep-2020
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De Matteis Tde Fine Licht JBeránek JHoefler TTaufer MBalaji PPeña A(2019)Streaming message interfaceProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3295500.3356201(1-33)Online publication date: 17-Nov-2019
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Youhui ZYouyang ZYanhua LXiang FWeimin Z(2017)In-Place Irregular Computation for Message-Passing Chip-Multiprocessors2017 46th International Conference on Parallel Processing Workshops (ICPPW)10.1109/ICPPW.2017.23(69-76)Online publication date: Aug-2017
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