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Progressive hashing for packet processing using set associative memory

Published: 19 October 2009 Publication History
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  • Abstract

    As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing engine is a critical part of the Internet router as it is used to perform packet forwarding (PF) and packet classification (PC). In both applications, processing has to be at wire speed. It is common to use hash-based schemes in packet processing engines; however, the downside of classic hashing techniques such as overflow and worst case memory access time, has to be dealt with. Implementing hash tables using set associative memory has the property that each bucket of a hash table can be searched in one memory cycle outperforming the conventional Ternary CAMs in terms of power and scalability.
    In this paper we present "Progressive Hashing" (PH), a general open addressing hash-based packet processing scheme for Internet routers using the set associative memory architecture. Our scheme is an extension of the multiple hashing scheme and is amendable to high-performance hardware implementation with low overflow and low memory access latency. We show by experimenting with real IP lookup tables and synthetic packet filtering databases that PH reduces the overflow over the multiple hashing. The proposed PH processing engine is estimated to achieve an average processing speed of 160 Gbps for the PC application and 320 Gbps for the PF application.

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    • (2021)Hardware Acceleration of Hash Operations in Modern MicroprocessorsIEEE Transactions on Computers10.1109/TC.2020.301085570:9(1412-1426)Online publication date: 1-Sep-2021
    • (2021)CP-Trie: Cumulative PopCount based Trie for IPv6 Routing Table Lookup in Software and ASIC2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)10.1109/HPSR52026.2021.9481816(1-8)Online publication date: 7-Jun-2021
    • (2017)Circuit Level Design of a Hardware Hash Unit for use in Modern MicroprocessorsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060451(101-106)Online publication date: 10-May-2017
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      cover image ACM Conferences
      ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
      October 2009
      227 pages
      ISBN:9781605586304
      DOI:10.1145/1882486
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 19 October 2009

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      Author Tags

      1. architecture
      2. hardware hash
      3. packet classification
      4. packet forwarding

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      Cited By

      View all
      • (2021)Hardware Acceleration of Hash Operations in Modern MicroprocessorsIEEE Transactions on Computers10.1109/TC.2020.301085570:9(1412-1426)Online publication date: 1-Sep-2021
      • (2021)CP-Trie: Cumulative PopCount based Trie for IPv6 Routing Table Lookup in Software and ASIC2021 IEEE 22nd International Conference on High Performance Switching and Routing (HPSR)10.1109/HPSR52026.2021.9481816(1-8)Online publication date: 7-Jun-2021
      • (2017)Circuit Level Design of a Hardware Hash Unit for use in Modern MicroprocessorsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060451(101-106)Online publication date: 10-May-2017
      • (2017)An FPGA-Based Coprocessor for Hash Unit Acceleration2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.53(301-304)Online publication date: Nov-2017
      • (2016)A novel hardware hash unit design for modern microprocessors2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753316(412-415)Online publication date: Oct-2016
      • (2012)FlashTrieIEEE/ACM Transactions on Networking10.1109/TNET.2012.218864320:4(1262-1275)Online publication date: 1-Aug-2012
      • (2011)A novel scalable IPv6 lookup scheme using compressed pipelined triesProceedings of the 10th international IFIP TC 6 conference on Networking - Volume Part I10.5555/2008780.2008820(406-419)Online publication date: 9-May-2011
      • (2011)A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined TriesNETWORKING 201110.1007/978-3-642-20757-0_32(406-419)Online publication date: 2011

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