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Co-match: fast and efficient packet inspection for multiple flows

Published: 19 October 2009 Publication History

Abstract

Packet inspection is widely employed in application-layer protocol analyzing systems to enable accurate protocol identification. Many existing systems, however, fail to meet the requirement of keeping up with wire speed in networking. There are two limitations: (1) software-based matching schemes are usually in a sequential manner which is slow and inefficient; (2) fast hardware-based matching schemes are inapplicable to network packet processing for lacking of intrinsic support for multiple flows.
This paper proposes a novel approach for application-layer protocol identification called Co-Match, which combines software and hardware together to achieve fast and efficient signature matching for multiple flows. First, a grouping scheme is adopted to organize signatures into several matching sets. With this scheme, each packet is only matched against a subset of signatures, bringing about a remarkable improvement of matching speed in software. Second, an FPGA-based coprocessor is developed in order to support fast parallel regular expression matching for multiple flows in hardware. Moreover, a hardware-based flow-level traffic load balancer is employed to parallel multi-flow processing on multiple CPU cores. Experimental results show that our approach is efficient to handle multiple flows while system throughput can achieve the wire speed of Gigabit Ethernet links with moderate CPU usage.

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Cited By

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  • (2020)A Survey on FPGA Support for the Feasible Execution of Virtualized Network FunctionsIEEE Communications Surveys & Tutorials10.1109/COMST.2019.294369022:1(504-525)Online publication date: 1-Jan-2020
  • (2013)An Embedded NIDS with Multi-core Aware Packet CaptureProceedings of the 2013 IEEE 16th International Conference on Computational Science and Engineering10.1109/CSE.2013.119(778-785)Online publication date: 3-Dec-2013
  • (2011)Exploring and Enhancing the Performance of Parallel IDS on Multi-core ProcessorsProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.86(673-680)Online publication date: 16-Nov-2011

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    cover image ACM Conferences
    ANCS '09: Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
    October 2009
    227 pages
    ISBN:9781605586304
    DOI:10.1145/1882486
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 19 October 2009

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    Author Tags

    1. FPGA
    2. application-layer protocol identification
    3. deep packet inspection
    4. multi-core
    5. regular expression

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    View all
    • (2020)A Survey on FPGA Support for the Feasible Execution of Virtualized Network FunctionsIEEE Communications Surveys & Tutorials10.1109/COMST.2019.294369022:1(504-525)Online publication date: 1-Jan-2020
    • (2013)An Embedded NIDS with Multi-core Aware Packet CaptureProceedings of the 2013 IEEE 16th International Conference on Computational Science and Engineering10.1109/CSE.2013.119(778-785)Online publication date: 3-Dec-2013
    • (2011)Exploring and Enhancing the Performance of Parallel IDS on Multi-core ProcessorsProceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2011.86(673-680)Online publication date: 16-Nov-2011

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