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Applications of slack neighborhood graphs to timing driven optimization problems in FPGAs

Authors:

Anmol Mathur,

K. C. Chen,

C. L. LiuAuthors Info & Claims

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Pages 118 - 124

https://doi.org/10.1145/201310.201329

Published: 15 February 1995 Publication History

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Abstract

In this paper we examine three different problems related to FPGA placement: timing driven placement of a technology mapped circuit, timing driven reconfiguration for yield enhancement and fault tolerance in FPGAs and timing driven design re-engineering for FPGAs. We show that timing driven relocation which transforms an infeasible placement into a feasible one is a key problem the solution of which will lead to good algorithms for all three of these optimization problems. We introduce the concept of a slack neighborhood graph (SNG) as a general tool for timing driven relocation of modules in an infeasible placement with a bounded increase in critical path delay. The slack neighborhood graph approach provides a unified approach to the solution of three timing driven optimization problems of interest in this paper.

References

[1]

T. GAO, P. M. VAIDYA, C. L. L~V, A Performance Driven Macro-Cell Placement Algorithm, Proc. 29th DA C, 1992, pp. 1~ 7-152.

Digital Library

Google Scholar

[2]

A. V. GOLDBERG, An Efficient Implementation of a Scaling Minimum-Cost Flow Algorithm, Technical Report STAN-CS-92-1~39, Computer Science Department, Stanford University, Stanford, CA, 1992.

Google Scholar

[3]

N. J. HOWARD, A. M. TYRRELL, N. M. ALLINSON, The Yield Enhancement of Field-Programmable Gate Arrays, IEEE Trans. on VLSI Systems, Vol. 2, OJ 1994, pp. 115-123.

Digital Library

Google Scholar

[4]

A. MATHUR, C. L. L~u, Compression-Relaxation: A New Approach to Performance Driven Placement for Regular Architectures, Proc. Intl. Conf. on Computer- Aided Design, 1994, pp.130-136.

Digital Library

Google Scholar

[5]

A. MATHUR, C. L. L~u, Timing Driven Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs, submitted for publication, 1994.

Google Scholar

[6]

R. NAIR, C. L. BERMAN, P. S. HAUGE, E. J. YOFFA, Generation of Performance Constraints for Layout, IEEE Trans. on Computer-Aided Design, Vol. 8, Aug. 1989, pp. 860-874.

Digital Library

Google Scholar

[7]

J. NARASIMHAN, K. NAKAJIMA, C. S. RIM, A. T. DAHBURA, Yield Enhancement of Programmable ASIC Arrays by Reconfiguration of Circuit Placements, IEEE Trans. on Computer-Aided Design, Vol. 13, Aug. 1994, pp. 976-986.

Digital Library

Google Scholar

[8]

B. CODENOTT~, R. TAMASS~A, A Network Flow Approach to the Reconfiguration of VLSI Arrays, IEEE Transactions on Computers, 40 (1991), pp. 113-121.

Digital Library

Google Scholar

Cited By

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Kaptanoglu S(1996)Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channelsProceedings of Custom Integrated Circuits Conference10.1109/CICC.1996.510571(341-344)Online publication date: 1996
https://doi.org/10.1109/CICC.1996.510571
Mathur AChen KLiu CRudell R(1995)Re-engineering of timing constrained placements for regular architecturesProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225097(485-490)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225097
Mathur AChen KLiu C(1995)Re-engineering of timing constrained placements for regular architecturesProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480161(485-490)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480161

Index Terms

Applications of slack neighborhood graphs to timing driven optimization problems in FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

February 1995

174 pages

ISBN:089791743X

DOI:10.1145/201310

Chairmen:
Pak K. Chan
Univ. of California at Santa Cruz, Santa Cruz
,
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1995

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FPGA95

Sponsor:

SIGDA

FPGA95: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 12 - 14, 1995

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

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Kaptanoglu S(1996)Fast and accurate delay estimation for use in timing driven layout for FPGAs with segmented channelsProceedings of Custom Integrated Circuits Conference10.1109/CICC.1996.510571(341-344)Online publication date: 1996
https://doi.org/10.1109/CICC.1996.510571
Mathur AChen KLiu CRudell R(1995)Re-engineering of timing constrained placements for regular architecturesProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225097(485-490)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225097
Mathur AChen KLiu C(1995)Re-engineering of timing constrained placements for regular architecturesProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480161(485-490)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480161

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