research-article

Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems

Authors:

Abdoulaye Gamatie,

Laure GonnordAuthors Info & Claims

ACM SIGPLAN Notices, Volume 46, Issue 5

Pages 71 - 80

https://doi.org/10.1145/2016603.1967688

Published: 11 April 2011 Publication History

Abstract

In this paper, we propose a sound abstraction for an efficient static analysis of synchronous programs describing multi-clock embedded systems in Signal. This abstraction combines the Boolean theory and numeric interval approximation to adequately address clock relations defined as combinations of logical and numerical expressions. Through a few examples, we show how the proposed solution is used to determine absence of reaction captured by empty clocks; mutual exclusion captured by two or more clocks whose associated signals never occur at the same time; or hierarchical control of component activations via clock inclusion. We also show this analysis improves the quality of the code generated automatically by the Signal compiler, e.g., a code with smaller footprint, or a code executed more efficiently thanks to optimizations enabled by the new abstraction.

References

[1]

G. Alefeld and J. Hertzberger. Introduction to Interval Computation. Academic Press, NY, 1983.

[2]

T. Amagbegnon, L. Besnard, and P. Le Guernic. Arborescent canonical form of Boolean expressions. Technical Report 2290, INRIA, June 1994. URL www.inria.fr/rrrt/rr-2290.html.

[3]

C. Barrett, S. Ranise, A. Stump, and C. Tinelli. The Satisfiability Modulo Theories Library (SMT-LIB). www.SMT-LIB.org, 2008.

[4]

A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. The synchronous languages twelve years later. In Special issue on Embedded Systems, IEEE, 2003.

[5]

G. Berry. The foundations of ESTEREL. In Proof, Language and Interaction: Essays in Honour of Robin Milner. MIT Press, 2000.

Digital Library

[6]

F. Besson, T. Jensen, and J.-P. Talpin. Polyhedral analysis for synchronous languages. In Proceedings of the 6th International Symposium on Static Analysis, volume 1694 of Lecture Notes in Computer Science, pages 51--68. Springer-Verlag, September 1999.

Digital Library

[7]

A. Biere, A. Biere, M. Heule, H. van Maaren, and T. Walsh. Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications. IOS Press, Amsterdam, The Netherlands, 2009.

Digital Library

[8]

R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE transactions on computers, C-35(8):677--691, August 1986.

Digital Library

[9]

D. Chapiro. Globally Asynchronous Locally Synchronous Systems. PhD thesis, Stanford University, 1984.

Digital Library

[10]

P. Cousot and R. Cousot. Static determination of dynamic properties of programs. In Proceedings of the Second International Symposium on Programming, pages 106--130. Dunod, Paris, France, 1976.

[11]

R. Cytron, J. Ferrante, B. K. Rosen, M. N.Wegman, and F. K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. ACM Trans. Program. Lang. Syst., 13:451--490, October 1991. ISSN 0164-0925.

Digital Library

[12]

L. de Moura and N. Bjorner. Satisfiability Modulo Theories: An Appetizer. In Brazilian Symposium on Formal Methods (SBMF'2009), Gramado, Brazil, August 2009.

Digital Library

[13]

B. Dutertre and L. de Moura. Yices sat-solver. http://yices.csl.sri.com/, 2009.

[14]

J. Ferrante, K. J. Ottenstein, and J. D. Warren. The program dependence graph and its use in optimization. ACM Trans. Program. Lang. Syst., 9:319--349, July 1987. ISSN 0164-0925.

Digital Library

[15]

A. Gamati&#233;. Designing Embedded Systems with the SIGNAL Programming Language: Synchronous, Reactive Specification. Springer, New York, 2009. ISBN 978-1-4419-0940-4.

Digital Library

[16]

A. Gamati&#233;, T. Gautier, and P. Le Guernic. Towards static analysis of SIGNAL programs using interval techniques. In Synchronous Languages, Applications, and Programming (SLAP'06), March 2006.

[17]

A. Gamati&#233;, T. Gautier, and L. Besnard. An Interval-Based Solution for Static Analysis in the SIGNAL Language. In 15th IEEE Conference andWorkshop on Engineering of Computer Based Systems (ECBS'2008), Belfast, Northern Ireland, pages 182--190, April 2008.

Digital Library

[18]

L. Gonnord and N. Halbwachs. Abstract acceleration to improve precision of linear relation analysis. Research report, Verimag, 03 2010. URL http://laure.gonnord.org/pro/papers/rr-verimag10.pdf.

[19]

G. Hagen and C. Tinelli. Scaling up the formal verification of LUSTRE programs with smt-based techniques. In FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, pages 1--9, Piscataway, NJ, USA, 2008. IEEE Press. ISBN 978-1-4244-2735-2.

Digital Library

[20]

N. Halbwachs. A synchronous language at work: the story of LUSTRE. In 3th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'05), Verona, Italy, july 2005.

Digital Library

[21]

N. Halbwachs, F. Lagnier, and C. Ratel. Programming and verifying real-time systems by means of the synchronous data-flow programming language LUSTRE. IEEE Transactions on Software Engineering, 18(9):785--793, September 1992.

Digital Library

[22]

N. Halbwachs, Y.-E. Proy, and P. Roumanoff. Verification of real-time systems using linear relation analysis. Formal Methods in System Design: An International Journal, 11(2):157--185, August 1997.

Digital Library

[23]

B. Jeannet. Dynamic partitioning in linear relation analysis. application to the verification of reactive systems. Formal Methods in System Design, 23(1):5--37, July 2003.

Digital Library

[24]

G. Lalire, M. Argoud, and B. Jeannet. Interproc : an interprocedural analyzer for imparative languages. http://pop-art.inrialpes.fr/people/bjeannet/bjeannet-forge/interproc, 2009.

[25]

P. Le Guernic and T. Gautier. Advanced Topics in Data-Flow Computing, chapter Data-Flow to von Neumann: the SIGNAL approach, pages 413--438. Prentice-Hall, J.-L. Gaudiot and L. Bic eds., 1991.

[26]

P. Le Guernic, J.-P. Talpin, and J.-C. Le Lann. Polychrony for System Design. Journal for Circuits, Systems and Computers, 12(3):261--304, April 2003.

[27]

G. Magklis, G. Semeraro, D. Albonesi, S. Dropsho, S. Dwarkadas, and M. Scott. Dynamic frequency and voltage scaling for a multipleclock- domain microprocessor. Micro, IEEE, 23(6):62--68, November 2003. ISSN 0272-1732.

Digital Library

[28]

J. Muttersbach, T. Villiger, and W. Fichtner. Practical design of globally asychronous locally synchronous systems. In International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'00), pages 52--61, 2000.

Digital Library

[29]

M. Nebut. Specification and analysis of synchronous reactions. Formal Aspects of Computing, 16(3):263--291, august 2004.

[30]

A. Stump and M. Deters. The SMT-COMP 2009 Website, 2009. http://www.smtcomp.org/2009.

Cited By

Aguado JMendler MHanxleden RFuhrmann I(2019)Denotational fixed-point semantics for constructive scheduling of synchronous concurrencyActa Informatica10.1007/s00236-015-0238-x52:4-5(393-442)Online publication date: 2-Jan-2019
https://dl.acm.org/doi/10.1007/s00236-015-0238-x
Ngo VTalpin JGautier TGuernic PBesnard L(2013)Formal verification of synchronous data-flow program transformations toward certified compilersFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-013-3910-87:5(598-616)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1007/s11704-013-3910-8
Ngo VTalpin JGautier TBesnard LLe Guernic PCorporaal HStuijk S(2015)Modular translation validation of a full-sized synchronous compiler using off-the-shelf verification toolsProceedings of the 18th International Workshop on Software and Compilers for Embedded Systems10.1145/2764967.2775291(109-112)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1145/2764967.2775291
Show More Cited By

Index Terms

Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems
1. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Formal software verification
  2. Software organization and properties
    1. Software functional properties
      1. Correctness
      2. Formal methods
2. Theory of computation
  1. Logic
    1. Proof theory

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Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 46, Issue 5

LCTES '10

May 2011

170 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/2016603

Issue’s Table of Contents

LCTES '11: Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
April 2011
182 pages
ISBN:9781450305556
DOI:10.1145/1967677
General Chair:
Jan Vitek
Purdue University, USA
,
Program Chair:
Bjorn De Sutter
Ghent University, Belgium

Copyright © 2011 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 April 2011

Published in SIGPLAN Volume 46, Issue 5

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Cited By

Aguado JMendler MHanxleden RFuhrmann I(2019)Denotational fixed-point semantics for constructive scheduling of synchronous concurrencyActa Informatica10.1007/s00236-015-0238-x52:4-5(393-442)Online publication date: 2-Jan-2019
https://dl.acm.org/doi/10.1007/s00236-015-0238-x
Ngo VTalpin JGautier TGuernic PBesnard L(2013)Formal verification of synchronous data-flow program transformations toward certified compilersFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-013-3910-87:5(598-616)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1007/s11704-013-3910-8
Ngo VTalpin JGautier TBesnard LLe Guernic PCorporaal HStuijk S(2015)Modular translation validation of a full-sized synchronous compiler using off-the-shelf verification toolsProceedings of the 18th International Workshop on Software and Compilers for Embedded Systems10.1145/2764967.2775291(109-112)Online publication date: 1-Jun-2015
https://dl.acm.org/doi/10.1145/2764967.2775291
Ngo VTalpin JGautier TLe Guernic P(2015)Translation Validation for Clock Transformations in a Synchronous CompilerCompiler Construction10.1007/978-3-662-46675-9_12(171-185)Online publication date: 2015
https://doi.org/10.1007/978-3-662-46675-9_12
Suenaga KSekine HHasuo I(2013)Hyperstream processing systemsACM SIGPLAN Notices10.1145/2480359.242912048:1(417-430)Online publication date: 23-Jan-2013
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Geuns SHausmans JBekooij M(2013)Sequential specification of time-aware stream processing applicationsACM Transactions on Embedded Computing Systems10.1145/2435227.243523112:1s(1-19)Online publication date: 21-Mar-2013
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Suenaga KSekine HHasuo IGiacobazzi RCousot R(2013)Hyperstream processing systemsProceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages10.1145/2429069.2429120(417-430)Online publication date: 23-Jan-2013
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Jose BGamatie AOuy JShukla S(2011)SMT based false causal loop detection during code synthesis from Polychronous specificationsProceedings of the Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2011.5970517(109-118)Online publication date: 1-Jul-2011
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