research-article

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion

Authors:

Josep Maria Codina,

Antonio GonzálezAuthors Info & Claims

CF '11: Proceedings of the 8th ACM International Conference on Computing Frontiers

Article No.: 1, Pages 1 - 10

https://doi.org/10.1145/2016604.2016606

Published: 03 May 2011 Publication History

Abstract

In this paper we propose SoftHV, a high-performance HW/SW co-designed in-order processor that performs horizontal and vertical fusion of instructions.

SoftHV consists of a co-designed virtual machine (Cd-VM) which reorders, removes and fuses instructions from frequently executed regions of code. On the hardware front, SoftHV implements HW features for efficient execution of Cd-VM and efficient execution of the fused instructions. In particular, (1) Interlock Collapsing ALU (ICALU) are included to execute pairs of dependent simple arithmetic operations in a single cycle, and (2) Vector Load units (VLDU) are added to execute parallel loads.

The key novelty of SoftHV resides on the efficient usage of HW using a Cd-VM in order to provide high-performance by drastically cutting down processor complexity. Co-designed processor provides efficient mechanisms to exploit ILP and reduce the latency of certain code sequences.

Results presented in this paper show that SoftHV produces average performance improvements of 85% in SPECFP and 52% in SPECINT, and up-to 2.35x, over a conventional four-way in-order processor. For a two-way in-order processor configuration SoftHV obtains improvements in performance of 72% and 47% for SPECFP and SPECINT, respectively. Overall, we show that such a co-designed processor based on an in-order core provides a compelling alternative to out-of-order processors for the low-end domain where high-performance at a low-complexity is a key feature.

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Cited By

Wirsch RHochberger C(2021)Towards Transparent Dynamic Binary Translation from RISC-V to a CGRAArchitecture of Computing Systems10.1007/978-3-030-81682-7_8(118-132)Online publication date: 15-Jul-2021
https://doi.org/10.1007/978-3-030-81682-7_8
Watkins MNowatzki TCarno A(2016)Software transparent dynamic binary translation for coarse-grain reconfigurable architectures2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446060(138-150)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446060
Hoy CGovindarajuz VNowatzki TNagaraju RMarzec ZAgarwal PFrericks CCofell RSankaralingam K(2015)Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2015.7095806(203-214)Online publication date: Mar-2015
https://doi.org/10.1109/ISPASS.2015.7095806
Show More Cited By

Index Terms

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion
1. Computer systems organization
  1. Architectures
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

cover image ACM Conferences

CF '11: Proceedings of the 8th ACM International Conference on Computing Frontiers

May 2011

268 pages

ISBN:9781450306980

DOI:10.1145/2016604

General Chair:
Calin Cascaval
Qualcomm Research
,
Program Chairs:
Pedro Trancoso
University of Cyprus, CY
,
Viktor Prasanna
University of Southern California

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 May 2011

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CF'11: Computing Frontiers Conference

May 3 - 5, 2011

Ischia, Italy

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Overall Acceptance Rate 273 of 785 submissions, 35%

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Cited By

Wirsch RHochberger C(2021)Towards Transparent Dynamic Binary Translation from RISC-V to a CGRAArchitecture of Computing Systems10.1007/978-3-030-81682-7_8(118-132)Online publication date: 15-Jul-2021
https://doi.org/10.1007/978-3-030-81682-7_8
Watkins MNowatzki TCarno A(2016)Software transparent dynamic binary translation for coarse-grain reconfigurable architectures2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446060(138-150)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446060
Hoy CGovindarajuz VNowatzki TNagaraju RMarzec ZAgarwal PFrericks CCofell RSankaralingam K(2015)Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS.2015.7095806(203-214)Online publication date: Mar-2015
https://doi.org/10.1109/ISPASS.2015.7095806
Nowatzki TSartin-Tarm MDe Carli LSankaralingam KEstan CRobatmili B(2014)A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving TheoriesACM Transactions on Programming Languages and Systems10.1145/265899337:1(1-30)Online publication date: 17-Nov-2014
https://dl.acm.org/doi/10.1145/2658993
Nowatzki TFerris MSankaralingam KEstan CVaish NWood D(2013)Optimization and Mathematical Modeling in Computer ArchitectureSynthesis Lectures on Computer Architecture10.2200/S00531ED1V01Y201308CAC0268:4(1-144)Online publication date: 30-Sep-2013
https://doi.org/10.2200/S00531ED1V01Y201308CAC026
Nowatzki TSartin-Tarm MDe Carli LSankaralingam KEstan CRobatmili B(2013)A general constraint-centric scheduling framework for spatial architecturesACM SIGPLAN Notices10.1145/2499370.246216348:6(495-506)Online publication date: 16-Jun-2013
https://dl.acm.org/doi/10.1145/2499370.2462163
McFarlin DTucker CZilles C(2013)Discerning the dominant out-of-order performance advantageACM SIGPLAN Notices10.1145/2499368.245114348:4(241-252)Online publication date: 16-Mar-2013
https://dl.acm.org/doi/10.1145/2499368.2451143
Nowatzki TSartin-Tarm MDe Carli LSankaralingam KEstan CRobatmili BBoehm HFlanagan C(2013)A general constraint-centric scheduling framework for spatial architecturesProceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/2491956.2462163(495-506)Online publication date: 16-Jun-2013
https://dl.acm.org/doi/10.1145/2491956.2462163
McFarlin DTucker CZilles C(2013)Discerning the dominant out-of-order performance advantageACM SIGARCH Computer Architecture News10.1145/2490301.245114341:1(241-252)Online publication date: 16-Mar-2013
https://dl.acm.org/doi/10.1145/2490301.2451143
McFarlin DTucker CZilles CSarkar VBodik R(2013)Discerning the dominant out-of-order performance advantageProceedings of the eighteenth international conference on Architectural support for programming languages and operating systems10.1145/2451116.2451143(241-252)Online publication date: 16-Mar-2013
https://dl.acm.org/doi/10.1145/2451116.2451143
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