research-article

Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization

Authors:

Angelo G. da Luz,

Eduardo A. C. da Costa,

Marilton S. de AguiarAuthors Info & Claims

SBCCI '11: Proceedings of the 24th symposium on Integrated circuits and systems design

Pages 91 - 96

https://doi.org/10.1145/2020876.2020898

Published: 30 August 2011 Publication History

Abstract

This paper proposes the exploration of different heuristic-based algorithms for the best ordering and partitioning of coefficients in Finite Impulse Response (FIR) filters. Due to the characteristics of the FIR filter algorithms, which involve multiplications of input data with appropriate coefficients, the best ordering and partitioning of these operations can contribute for the reduction of the switching activity, what leads to the minimization of power consumption in the filters. Two heuristic-based algorithms named Nearest neighbor and Bellmore and Nemhauser are used in the tests. A new heuristic-based algorithm named Anedma is proposed to get as near as possible to the optimal solution for the ordering and partitioning of larger filter instances. Two set of coefficients were used for the tests, and the results are presented in terms of the Hamming distance between the consecutive coefficients. Sequential and semi-parallel FIR filter architectures were implemented with the coefficients ordered and partitioned. As will be shown, depending on the set of coefficients used, based on the guidance given by the heuristic algorithms, the power consumption of the FIR filter architectures can be reduced significantly.

References

[1]

M. Mehendale, S. Sherlekar, G. Venkatesh. Low Power Realization of FIR Filters on Programmable DSP's. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):546--553. December 1998.

Digital Library

[2]

A. Erdogan and T. Arslan. High Throughput FIR Filter Design for Low Power SOC Applications. In: 13th Annual IEEE International ASIC/SOC Conference, pp. 21--24. 2000.

[3]

M. Mehendale, S. Sherlekar, G. Venkatesh. Techniques for Low Power Realization of FIR Filters. In: Asia and South Pacific Design Automation Conference, ASPDAC, 1995. Proceedings & New York: ACM, 1995. pp. 447--450.

Digital Library

[4]

E. Costa, J. Monteiro, and S. Bampi. Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. In: 11th IEEE/IFIP International Conference on Very Large Scale Integration. VLSI-SoC. 2003.

[5]

E. Costa.; P. Flores; J. Monteiro, J. Maximal Sharing of Partial Terms in MCM under Minimal Signed Digit Representation. In: European Conference on Circuit Theory and Design. pp. 221--224. 2005.

[6]

V. S. Rosa. Uma Ferramenta Para a Geração Otimizada de Filtros FIR paralelos Com Coeficientes Constantes. Dissertação de Mestrado. 2005.

[7]

M. Mehendale, S. Sherlekar, and G. Venkatesh. Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. In: 11th Int. Conf. on VLSI Design. p. 12--17. 1998.

Digital Library

[8]

A. Erdogan, and T. Arslan. Low Power FIR Implementations Based on Coefficient Ordering Algorithm. In: International Symposium on VLSI. 2004.

[9]

Ansari, Nirwan and Hou, E. Computational Intelligence for Optimization. Kluwer Academic Publishers, 1997.

[10]

Reeves, C.R. Modern Heuristic Techniques for Combinatorial Problems. Blackwell Scientif Publications, 1993.

Digital Library

[11]

Sequential interactive system. Available: http://embedded.eecs.berkeley.edu/pubs/downloads/sis/index.htm

[12]

Switch-level simulator webpage. {Online}. Available: http://www.space.tudelft.n1/

[13]

E. Costa, S. Bampi, and J. Monteiro. A New Architecture for Signed Radix-2m Pure Array Multipliers. In: 20th International Conference on Computer Design -- ICCD. pp. 112--117. 2002.

Digital Library

[14]

L. Pieper, et al. Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers. Journal of Computers, v.5, pp. 1502--1509, 2010.

[15]

A. Luz, E. Costa, M. Aguiar. Ordering and Partitioning of Coefficients Based on Heuristics Algorithms for Low Power FIR Filter Realization. In: 23th Symposium on Integrated Circuits and Systems Design. pp. 180--185. 2010.

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Cited By

Ghissoni Sda Costa Eda Luz A(2014)Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2014.7004162(1-6)Online publication date: Oct-2014
https://doi.org/10.1109/VLSI-SoC.2014.7004162
Rahmeier JLuz ACosta EGhissoni S(2013)Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS.2013.6815338(33-36)Online publication date: Dec-2013
https://doi.org/10.1109/ICECS.2013.6815338
da Luz Ada Costa EGhissoni S(2012)Reducing power consumption in FFT architectures by using heuristic-based algorithms for the ordering of the twiddle factors2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS.2012.6180313(1-4)Online publication date: Feb-2012
https://doi.org/10.1109/LASCAS.2012.6180313

Index Terms

Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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cover image ACM Conferences

SBCCI '11: Proceedings of the 24th symposium on Integrated circuits and systems design

August 2011

244 pages

ISBN:9781450308281

DOI:10.1145/2020876

General Chair:
Antonio Carlos Cavalcanti
Federal University of Paraíba, Brazil
,
Program Chairs:
Elmar Uwe Kurl Melcher
Federal University of Campina Grande, Brazil
,
Jürgen Becker
Karlsruhe Institute of Technology (KIT), DE

Copyright © 2011 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 August 2011

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SBCCI '11: 24th Symposium on Integrated Circuits and Systems Design

August 30 - September 2, 2011

João Pessoa, Brazil

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Cited By

Ghissoni Sda Costa Eda Luz A(2014)Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2014.7004162(1-6)Online publication date: Oct-2014
https://doi.org/10.1109/VLSI-SoC.2014.7004162
Rahmeier JLuz ACosta EGhissoni S(2013)Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS.2013.6815338(33-36)Online publication date: Dec-2013
https://doi.org/10.1109/ICECS.2013.6815338
da Luz Ada Costa EGhissoni S(2012)Reducing power consumption in FFT architectures by using heuristic-based algorithms for the ordering of the twiddle factors2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS.2012.6180313(1-4)Online publication date: Feb-2012
https://doi.org/10.1109/LASCAS.2012.6180313

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