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Can we go towards true 3-D architectures?

Published: 05 June 2011 Publication History
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  • Abstract

    Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored and its performance is evaluated. A comparison made on an equivalent technology node shows that our cells reduce area and delay by a factor of 31x and 2x respectively. Large reconfigurable logic circuits have been benchmarked showing an improvement of area and delay by 46% and 48% on average.

    References

    [1]
    G. Van der Plas et al., Design issues and considerations for low-cost 3D TSV IC technology, ISSCC, 2010.
    [2]
    M. Lin et al., Performance Benefits of Monolithically Stacked 3-D FPGA, IEEE TCAD, vol.26, no.2, 2007.
    [3]
    V. Renard et al., Catalyst preparation for CMOS-compatible silicon nanowire synthesis, Nature Nanotechnology, 2009.
    [4]
    J. Goldberger et al., Silicon Vertically Integrated Nanowire Field Effect Transistors, Nano Letters, Vol. 6, No 5, 2006.
    [5]
    K. Siozios et al., Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support, FPL, 2007.

    Cited By

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    • (2013)Reconfigurable architectures and emerging technologies2013 IEEE Faible Tension Faible Consommation10.1109/FTFC.2013.6577783(1-1)Online publication date: Jun-2013

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    1. Can we go towards true 3-D architectures?

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      cover image ACM Conferences
      DAC '11: Proceedings of the 48th Design Automation Conference
      June 2011
      1055 pages
      ISBN:9781450306362
      DOI:10.1145/2024724

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      Association for Computing Machinery

      New York, NY, United States

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      Published: 05 June 2011

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      Author Tags

      1. back-end
      2. logic gates
      3. nanowires

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      • (2013)Reconfigurable architectures and emerging technologies2013 IEEE Faible Tension Faible Consommation10.1109/FTFC.2013.6577783(1-1)Online publication date: Jun-2013

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