research-article

Performance of partial reconfiguration in FPGA systems: A survey and a cost model

Authors:

Kyprianos Papadimitriou,

Apostolos Dollas,

Scott HauckAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 4

Article No.: 36, Pages 1 - 24

https://doi.org/10.1145/2068716.2068722

Published: 28 December 2011 Publication History

Abstract

Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and with real experiments we produce a cost model of Partial Reconfiguration (PR). This model is introduced to calculate the expected reconfiguration time and throughput. In order to develop a realistic model we take into account all the physical components that participate in the reconfiguration process. We analyze the parameters that affect the generality of the model and the adjustments needed per system for error-free evaluation. We verify it with real measurements, and then we employ it to evaluate existing systems presented in previous publications. The percentage error of the cost model when comparing its results with the actual values of those publications varies from 36% to 63%, whereas existing works report differences up to two orders of magnitude. Present work enables a user to evaluate PR and decide whether it is suitable for a certain application prior entering the complex PR design flow.

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Cited By

Zhang GShao LWu HGu XZhang X(2025)Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable SystemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.346831772:1(268-272)Online publication date: Jan-2025
https://doi.org/10.1109/TCSII.2024.3468317
Khan LIsanaka SLiou F(2024)FPGA-Based Sensors for Distributed Digital Manufacturing Systems: A State-of-the-Art ReviewSensors10.3390/s2423770924:23(7709)Online publication date: 2-Dec-2024
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Liu FLi HHu WHe Y(2024)Review of neural network model acceleration techniques based on FPGA platformsNeurocomputing10.1016/j.neucom.2024.128511(128511)Online publication date: Aug-2024
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Index Terms

Performance of partial reconfiguration in FPGA systems: A survey and a cost model
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 4, Issue 4

December 2011

179 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2068716

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Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 December 2011

Accepted: 01 January 2011

Received: 01 December 2009

Published in TRETS Volume 4, Issue 4

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Cited By

Zhang GShao LWu HGu XZhang X(2025)Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable SystemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.346831772:1(268-272)Online publication date: Jan-2025
https://doi.org/10.1109/TCSII.2024.3468317
Khan LIsanaka SLiou F(2024)FPGA-Based Sensors for Distributed Digital Manufacturing Systems: A State-of-the-Art ReviewSensors10.3390/s2423770924:23(7709)Online publication date: 2-Dec-2024
https://doi.org/10.3390/s24237709
Liu FLi HHu WHe Y(2024)Review of neural network model acceleration techniques based on FPGA platformsNeurocomputing10.1016/j.neucom.2024.128511(128511)Online publication date: Aug-2024
https://doi.org/10.1016/j.neucom.2024.128511
Friesel BLütke Dreimann MSpinczyk O(2023)A Full-System Perspective on UPMEM PerformanceProceedings of the 1st Workshop on Disruptive Memory Systems10.1145/3609308.3625266(1-7)Online publication date: 23-Oct-2023
https://dl.acm.org/doi/10.1145/3609308.3625266
Mancuso RRoozkhosh SHoornaert DMun JPapon TAthanassoulis M(2023)Software-Shaped PlatformsProceedings of Cyber-Physical Systems and Internet of Things Week 202310.1145/3576914.3587546(185-191)Online publication date: 9-May-2023
https://dl.acm.org/doi/10.1145/3576914.3587546
Dann JRitter DFröning H(2023)Non-relational Databases on FPGAs: Survey, Design Decisions, ChallengesACM Computing Surveys10.1145/356899055:11(1-37)Online publication date: 9-Feb-2023
https://dl.acm.org/doi/10.1145/3568990
Valente GMuttillo VFederici FPomante LDi Mascio T(2023)Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic InjectionIEEE Embedded Systems Letters10.1109/LES.2023.330540116:2(162-165)Online publication date: 15-Aug-2023
https://dl.acm.org/doi/10.1109/LES.2023.3305401
Zhang JLi J(2023)Intelligent Navigation Satellite SystemIntelligent Satellite Design and Implementation10.1002/9781394198986.ch8(145-167)Online publication date: 13-Oct-2023
https://doi.org/10.1002/9781394198986.ch8
Bailey D(2023)Design ConstraintsDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch4(77-104)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch4
Wanta DSmolik WKryszyn JWróblewski PMidura M(2022)A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography SystemElectronics10.3390/electronics1104054511:4(545)Online publication date: 11-Feb-2022
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