research-article

Optimizing the antenna area and separators in layer assignment of multi-layer global routing

Authors:

Yih-Lang LiAuthors Info & Claims

ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

Pages 137 - 144

https://doi.org/10.1145/2160916.2160946

Published: 25 March 2012 Publication History

Abstract

Traditional solutions to antenna effect, such as jumper insertion and diode insertion peformed at post-route stage may produce extra vias and degrade circuit performance. The work in [1] suggests combining layer assignment, jumper insertion and diode insertion together to achieve a better design quality with less additional cost. Based on our observations on global and local antenna violations, this work proposes a dynamic-programming based single-net layer assignment called NALAR, which first enumerates all antenna-violation-safe layer assignment solutions of a net, and then extracts the minimum-cost one for the net. NALAR can minimize via count and separators as well. In addition, an antenna avoidance layer assignment algorithm (ANLA) adopting NALAR as its kernel not only avoids global antenna violations, but also eliminates local antenna violations. Experimental results reveal that, in 11 benchmarks, ANLA can yield 5 violation-free assignments while the algorithms of other works yield no violation-free assignment. As for the total number of antenna violations in all benchmarks, this work and the works in [2], [3] and [4] yield 21, 43506, 41261 and 29671 antenna violations, respectively. However, ANLA performs about 7 times slower than other antenna-aware layer assignment [4].

References

[1]

D. Wu, J. Hu, and R. Mahapatra, "Antenna avoidance in layer assignment," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 1643--1656, 2006.

Digital Library

[2]

T.-H. Lee, T.-C. Wang, "Congestion-constrained layer assignment for via minimization in global routing," IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pages 1643--1656, 2008.

Digital Library

[3]

Wen-Hao Liu and Yih-Lang Li, "Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization," in The 16th Asia and South Pacific Design Automation Conference, Jan. 2011, P. 539--544.

Digital Library

[4]

T.-H. Lee and T.-C. Wang, "Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing," Proc. Intl. Conf. on Computer-Aided Design, pp. 312--318, 2010.

Digital Library

[5]

J. A. Roy and I. L. Markov, "High-performance routing at the nanometer scale," IEEE Trans. on Computer-Aided Design, vol. 27, no. 6, pp. 1066--1077, 2008.

Digital Library

[6]

M. D. Moffitt, "MaizeRouter: Engineering an effective global router," in Proc. Asia and South Pacific Design Automation Conf., pages 232--237, 2008.

Digital Library

[7]

M. Cho, K. Lu, K. Yuan, and D. Z. Pan, "BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router," in Proc. Int. Conf. Comput.-Aided Des., pages 503--508, 2007

Digital Library

[8]

M. M. Ozdal and M. D.F. Wong, "ARCHER: A history-driven global routing algorithm," in Proc. Int. Conf. Comput.-Aided Des., pages 488--495, 2007.

Digital Library

[9]

Y.-J. Chang, Y.-T. Lee, and T.-C. Wang, "NTHU-Route 2.0: a fast and stable global router," in Proc. Int. Conf. Comput.-Aided Des., pages 338--343, 2008.

Digital Library

[10]

H.-Y. Chen, C.-H. Hsu, and Y.-W. Chang. "High-performance global routing with fast overflow reduction." in Proc. Asia and South Pacific Design Automation Conf., pages 582--587, 2009.

Digital Library

[11]

Y. Xu, Y. Zhang and C. Chu, "FastRoute 4.0: Global Router with Efficient Via Minimization," In Proc. Asia and South Pacific Design Automation Conf., pages 576--581, 2009.

Digital Library

[12]

K.-R. Dai, W.-H. Liu, and Y.-L. Li, "Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing," in Proc. Asia and South Pacific Design Automation Conf., pages 570--575, 2009.

Digital Library

[13]

W.-H. Liu, W.-C. Kao, Y.-L. Li and K.-Y. Chao, "Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing" in Proc. Des. Autom. Conf., pages. 200--205, June 2010.

Digital Library

[14]

N. J. Naclerio, S. Masuda, and K. Nakajima, "The via minimization problem is NP-complete," IEEE Trans. Comput, pages 1604--1608, Nov. 1989.

Digital Library

[15]

T.-H. Lee, T.-C. Wang, "Robust layer assignment for via optimization in multi-layer global routing," In Proc. Intl. Symp. On Physical Desgin, pages 159--166, 2009.

Digital Library

[16]

Z. Chen and I. Koren, "Layer reassignment for antenna effect minimization in 3-layer channel routing," in Proc. IEEE Int. Symp. Defect Fault Tolerance, Boston, MA, 1996, pp. 77--85.

Digital Library

[17]

H. Shin, C.-C. King, and C. Hu, "Thin Oxide Damage by Plasma Etching and Ashing Process," Proceedsings of International Reliability Physics Symposium, pp. 37--41, 1992.

[18]

H. Watanabe, J. Komori, K. Higashitani, M. Sekine, and H. Koyama,"A Wafer Level Monitoring Method for Plasma-charging Damage Using Antenna PMOSFET Test Structure," IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 2, pp. 228--232, 1997.

[19]

http://archive.sigda.org/ispd2008/contests/ispd08rc.html.

Cited By

Yu YLi ZChen JHuang XLiu GXu N(2024)Multi-Strategy Bus Deviation-Driven Layer Assignment Algorithm2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617851(456-461)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617851
Chiu WJiang ILu CChang Y(2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062303
Sheqin Dong Jianchang Ao Fuqi Luo (2015)Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect StructureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240487134:5(740-752)Online publication date: May-2015
https://doi.org/10.1109/TCAD.2015.2404871
Show More Cited By

Index Terms

Optimizing the antenna area and separators in layer assignment of multi-layer global routing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

Delay-driven layer assignment in global routing under multi-tier interconnect structure
ISPD '13: Proceedings of the 2013 ACM International symposium on Physical Design

A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the ...
Robust layer assignment for via optimization in multi-layer global routing
ISPD '09: Proceedings of the 2009 international symposium on Physical design

In this paper, we study a layer assignment problem which arises during multi-layer global routing. Our layer assignment problem takes the total wire overflow and the maximum wire overflow of a given 2D global routing solution to form the wire congestion ...
Coupling aware timing optimization and antenna avoidance in layer assignment
ISPD '05: Proceedings of the 2005 international symposium on Physical design

The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design

March 2012

220 pages

ISBN:9781450311670

DOI:10.1145/2160916

General Chair:
Jiang Hu
Texas A&M University
,
Program Chair:
Cheng-Kok Koh
Purdue University

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 March 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISPD'12

Sponsor:

SIGDA

ISPD'12: International Symposium on Physical Design

March 25 - 28, 2012

California, Napa, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
171
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Yu YLi ZChen JHuang XLiu GXu N(2024)Multi-Strategy Bus Deviation-Driven Layer Assignment Algorithm2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617851(456-461)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617851
Chiu WJiang ILu CChang Y(2017)Power and Area Efficient Hold Time Fixing by Free Metal Segment AllocationProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062303(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062303
Sheqin Dong Jianchang Ao Fuqi Luo (2015)Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect StructureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240487134:5(740-752)Online publication date: May-2015
https://doi.org/10.1109/TCAD.2015.2404871
Lin CLiu WLi Y(2014)Skillfully diminishing antenna effect in layer assignment stageTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test10.1109/VLSI-DAT.2014.6834859(1-4)Online publication date: Apr-2014
https://doi.org/10.1109/VLSI-DAT.2014.6834859
Ao JDong SChen SGoto SKoh CSze C(2013)Delay-driven layer assignment in global routing under multi-tier interconnect structureProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451942(101-107)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451942

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents