Marc Tremblay, "A fast and flexible performance simulator for microarchitecture trade-off analysis on UltraS- PARC", 32nd Design Automation Conference Proceedings (in press).

Digital Library

Google Scholar

[5]

S. Mehta, et. al., "Verification of the UltraSPARC Microprocessor", 40th annual Compcon, 1995.

Digital Library

Google Scholar

[6]

Palnitkar, Saggurati "Finite State Machine Coverage program" Open Verilog International Conf. 1994.

Google Scholar

[7]

L. Kohn, et. a/.,"The Visual Instruction Set (VIS) in UltraSPARC", 40th annual Compcon, 1995.

Digital Library

Google Scholar

[8]

C. Zhou, et. al., "MPEG Video Decoding with UltraS- PARC Visual instruction Set", 40th annual Compcon, 1995.

Digital Library

Google Scholar

[9]

James Gateley, "Logic emulation aids design process", ASIC & EDA, July 1994.

Google Scholar

[10]

James Gateley, Miriam B latt, "Reducing time-to-emulation through flow automation", Nikkei Electronics (in press).

Google Scholar

Cited By

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Athavale VHertz SJetly DGanesan VKrysl JVasudevan SJerraya ACarloni LChang NFummi F(2012)Using static analysis for coverage extraction fromemulation/prototyping platformsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380481(207-214)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380481
Sung WOu SLiu YChen C(2012)Employed VeriLite simulation to improve SOC design and verificationComputer Applications in Engineering Education10.1002/cae.2040420:2(374-382)Online publication date: 11-Apr-2012
https://doi.org/10.1002/cae.20404
Paya-Vay GMartin-Langerwerf JPirsch P(2007)RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341471(215-221)Online publication date: Aug-2007
https://doi.org/10.1109/DSD.2007.4341471
Show More Cited By

Index Terms

UltraSPARC-I
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
2. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Athavale VHertz SJetly DGanesan VKrysl JVasudevan SJerraya ACarloni LChang NFummi F(2012)Using static analysis for coverage extraction fromemulation/prototyping platformsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380481(207-214)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380481
Sung WOu SLiu YChen C(2012)Employed VeriLite simulation to improve SOC design and verificationComputer Applications in Engineering Education10.1002/cae.2040420:2(374-382)Online publication date: 11-Apr-2012
https://doi.org/10.1002/cae.20404
Paya-Vay GMartin-Langerwerf JPirsch P(2007)RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341471(215-221)Online publication date: Aug-2007
https://doi.org/10.1109/DSD.2007.4341471
Hosokawa KTanaka KNakamura Y(2007)Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1093/ietfec/e90-a.12.2810E90-A:12(2810-2817)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1093/ietfec/e90-a.12.2810
Nakamura Y(2006)Software Verification for System on a Chip using a C/C++ Simulator and FPGA Emulator2006 International Symposium on VLSI Design, Automation and Test10.1109/VDAT.2006.258142(1-4)Online publication date: Dec-2006
https://doi.org/10.1109/VDAT.2006.258142
Penry DFay DHodgdon DWells RSchelle GAugust DConnors D(2006)Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processorsThe Twelfth International Symposium on High-Performance Computer Architecture, 2006.10.1109/HPCA.2006.1598110(27-38)Online publication date: 2006
https://doi.org/10.1109/HPCA.2006.1598110
Spillane JOwen H(2005)Temporal partitioning for partially-reconfigurable-field-programmable gateParallel and Distributed Processing10.1007/3-540-64359-1_670(37-42)Online publication date: 8-Jun-2005
https://doi.org/10.1007/3-540-64359-1_670
Vayá GLangerwerf JPirsch P(2005)RAPANUIProceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11512622_5(32-40)Online publication date: 18-Jul-2005
https://dl.acm.org/doi/10.1007/11512622_5
Ohba NTakano KMalik SFix LKahng A(2004)An SoC design methodology using FPGAs and embedded microprocessorsProceedings of the 41st annual Design Automation Conference10.1145/996566.996769(747-752)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996769
Nakamura YHosokawa KKuroda IYoshikawa KYoshimura TMalik SFix LKahng A(2004)A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communicationProceedings of the 41st annual Design Automation Conference10.1145/996566.996655(299-304)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996655
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Performance Nonmonotonicities: A Case Study of the UltraSPARC Processor

Efficient Array Characterization in the UltraSPARC T2

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

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Performance Nonmonotonicities: A Case Study of the UltraSPARC Processor

Efficient Array Characterization in the UltraSPARC T2

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

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