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Analysis of switch-level faults by symbolic simulation

Authors:

Lluís Ribas-Xirgo,

Jordi Carrabina-BordollAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 352 - 357

https://doi.org/10.1145/217474.217554

Published: 01 January 1995 Publication History

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Cited By

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Ribas Xirgo LBordoll J(1999)Digital MOS circuit partitioning with symbolic modelingProceedings of the conference on Design, automation and test in Europe10.1145/307418.307552(103-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307552
Ribas Xirgo LCarrabina Bordoll J(1999)Digital MOS circuit partitioning with symbolic modelingDesign, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)10.1109/DATE.1999.761173(503-508)Online publication date: 1999
https://doi.org/10.1109/DATE.1999.761173
Ribas-Xirgo LCarrabina-Bordoll JDewilde PRammig FMusgrave G(1998)On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuitsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368316(624-631)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368316
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Index Terms

Analysis of switch-level faults by symbolic simulation
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Ordered binary decision diagrams for optimization in symbolic switch-level analysis of MOS circuits

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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Ribas Xirgo LBordoll J(1999)Digital MOS circuit partitioning with symbolic modelingProceedings of the conference on Design, automation and test in Europe10.1145/307418.307552(103-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307552
Ribas Xirgo LCarrabina Bordoll J(1999)Digital MOS circuit partitioning with symbolic modelingDesign, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)10.1109/DATE.1999.761173(503-508)Online publication date: 1999
https://doi.org/10.1109/DATE.1999.761173
Ribas-Xirgo LCarrabina-Bordoll JDewilde PRammig FMusgrave G(1998)On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuitsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368316(624-631)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368316
Ribas-Xirgo LCarrabina-Bordoll J(1998)On the reuse of symbolic simulation results for incremental equivalence verification of switch-level circuitsProceedings Design, Automation and Test in Europe10.1109/DATE.1998.655923(624-629)Online publication date: 1998
https://doi.org/10.1109/DATE.1998.655923
Ribas-Xirgo LCarrabina-Bordoll J(1996)Automatic test pattern generation for Iddq faults based upon symbolic simulationDigest of Papers 1996 IEEE International Workshop on IDDQ Testing10.1109/IDDQ.1996.557840(94-98)Online publication date: 1996
https://doi.org/10.1109/IDDQ.1996.557840

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A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults

Switch-Level Logic Simulation of Digital Bipolar Circuits

Ordered binary decision diagrams for optimization in symbolic switch-level analysis of MOS circuits

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A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults

Switch-Level Logic Simulation of Digital Bipolar Circuits

Ordered binary decision diagrams for optimization in symbolic switch-level analysis of MOS circuits

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