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Performance driven global routing and wiring rule generation for high speed PCBs and MCMs

Authors:

Sharad Mehrotra,

Paul Franzon,

Michael SteerAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 381 - 387

https://doi.org/10.1145/217474.217559

Published: 01 January 1995 Publication History

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References

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Cited By

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Lackey D(2000)Applying placement-based synthesis for on-time system-on-a-chip designProceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)10.1109/CICC.2000.852631(121-124)Online publication date: 2000
https://doi.org/10.1109/CICC.2000.852631
Cong JMadden PChawla BBryant RRabaey J(1998)Performance driven multi-layer general area routing for PCB/MCM designsProceedings of the 35th annual Design Automation Conference10.1145/277044.277144(356-361)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277144
Sheehan BPennino TYoffa E(1996)An AWE technique for fast printed circuit board delaysProceedings of the 33rd annual Design Automation Conference10.1145/240518.240620(539-543)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240620
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Performance driven global routing and wiring rule generation for high speed PCBs and MCMs
1. Hardware

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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Lackey D(2000)Applying placement-based synthesis for on-time system-on-a-chip designProceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)10.1109/CICC.2000.852631(121-124)Online publication date: 2000
https://doi.org/10.1109/CICC.2000.852631
Cong JMadden PChawla BBryant RRabaey J(1998)Performance driven multi-layer general area routing for PCB/MCM designsProceedings of the 35th annual Design Automation Conference10.1145/277044.277144(356-361)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277144
Sheehan BPennino TYoffa E(1996)An AWE technique for fast printed circuit board delaysProceedings of the 33rd annual Design Automation Conference10.1145/240518.240620(539-543)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240620
Sheehan B(1996)An AWE technique for fast printed circuit board delays33rd Design Automation Conference Proceedings, 199610.1109/DAC.1996.545634(539-543)Online publication date: 1996
https://doi.org/10.1109/DAC.1996.545634
Gupta RPileggi LRudell R(1995)Constrained multivariable optimization of transmission lines with general topologiesProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224871(130-137)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.224871
Gupta RPileggi L(1995)Constrained multivariable optimization of transmission lines with general topologiesProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480003(130-137)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480003

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Escape Routing for Staggered-Pin-Array PCBs

Escape routing for staggered-pin-array PCBs

Timing-constrained congestion-driven global routing

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Escape Routing for Staggered-Pin-Array PCBs

Escape routing for staggered-pin-array PCBs

Timing-constrained congestion-driven global routing

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