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Simultaneous gate and interconnect sizing for circuit-level delay optimization

Authors:

Noel Menezes,

Satyamurthy Pullela,

Lawrence T. PileggiAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 690 - 695

https://doi.org/10.1145/217474.217612

Published: 01 January 1995 Publication History

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References

[1]

J. Cong, and K.-S. Leung, "Optimal wiresizing under the distributed Elmore delay model," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1993.

Digital Library

Google Scholar

[2]

J. E Fishburn and A. E. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1985.

Google Scholar

[3]

D. Marple, "Transistor size optimization in the Tailor layout system," Proc. ACM/IEEE 26th Design Automation Conference, June 1989.

Digital Library

Google Scholar

[4]

S.S. Sapatnekar, et al., "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Computer-AidedDesign, vol. 12, no. 11, pp. 1621- 1634, May 1992.

Digital Library

Google Scholar

[5]

M. Marek-Sadowska and S. E Lin, "Timing-driven placement," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1989.

Google Scholar

[6]

K.D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, "Rectilinear Steiner Trees with minimum Elmore delay," Proc. 31st ACM/IEEE Design Automation Conference, June 1994.

Digital Library

Google Scholar

[7]

J. Cong, et al., "Provably good performance-driven global routing," IEEE Trans. Computer-Aided Design, vol. 11, no. 6, pp. 739 - 752, June 1992.

Crossref

Google Scholar

[8]

J. Cong and C.-K. Koh, "Simultaneous driver and wire sizing for performance and power optimization," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1994.

Digital Library

Google Scholar

[9]

S.S. Sapatnekar, "RC interconnect optimization under the Elmore delay model," Proc. 31st ACM/IEEE Design Automation Conference, June 1994.

Digital Library

Google Scholar

[10]

J. Rubenstein, E Penfield, Jr., and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.

Google Scholar

[11]

J. K. Ousterhout, "A switch-level timing verifier for digital MOS VLSI," IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 3, pp. 336-349, July 1985.

Google Scholar

[12]

J. Qian, S. Pullela, and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Computer- Aided Design, vol. 13, no. 12, pp. 1526-1535, December 1994.

Digital Library

Google Scholar

[13]

F. Dartu, N. Menezes, J. Qian, and L.T. Pillage, "A gate-delay model for high-speed CMOS circuits," Proc. 31st ACM/IEEE Design Automation Conference, June 1994.

Digital Library

Google Scholar

[14]

C.L. Ratzlaff, N. Gopal, and L.T. Pillage, "RICE: Rapid Interconnect Circuit Evaluator," Proc. 28th ACM/IEEE Design Automation Conference, June 1991.

Digital Library

Google Scholar

[15]

L.T. Pillage and R.A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 352-366, April 1990.

Digital Library

Google Scholar

[16]

N. Menezes, S. Pullela, F. Dartu, and L. T. Pillage, "RC interconnect synthesis-a moment fitting approach," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1994.

Digital Library

Google Scholar

[17]

Q. Zhu, W.-M. Dai, and J. G. Xi, "Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models," Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, November 1993.

Digital Library

Google Scholar

[18]

D. W. Marquardt, "An algorithm for least-squares estimation of nonlinear parameters," J. Soc. Indust. App. Math., vol. 11, no. 2, pp. 431 - 441, June 1963.

Crossref

Google Scholar

[19]

K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins, "Fidelity and near-optimality of Elmore-based routing constructions," Proc. IEEE/ACM Intl. Conf. Computer Design, November 1993.

Google Scholar

[20]

D. K. Ferry, "Interconnection lengths and VLSI," IEEE Circuits and Devices Magazine, 1, July 1985.

Crossref

Google Scholar

[21]

Wing Luk, "A fast physical constraint generator for timing driven layout," Proc. 28th ACM/IEEE Design Automation Conference, June 1991.

Digital Library

Google Scholar

Cited By

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Montiel-Nelson JSosa JNavarro HSarmiento RNunez A(2005)Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizingIEE Proceedings - Circuits, Devices and Systems10.1049/ip-cds:20040779152:2(133)Online publication date: 2005
https://doi.org/10.1049/ip-cds:20040779
Chen CChu CWong DYasuura H(1998)Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289097(617-624)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.289097
Cong JPan ZHe LKoh CKhoo KOtten RYasuura H(1997)Interconnect design for deep submicron ICsProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266534(478-485)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266534
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Simultaneous gate and interconnect sizing for circuit-level delay optimization
1. Hardware

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DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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June 12 - 16, 1995

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Montiel-Nelson JSosa JNavarro HSarmiento RNunez A(2005)Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizingIEE Proceedings - Circuits, Devices and Systems10.1049/ip-cds:20040779152:2(133)Online publication date: 2005
https://doi.org/10.1049/ip-cds:20040779
Chen CChu CWong DYasuura H(1998)Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289097(617-624)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.289097
Cong JPan ZHe LKoh CKhoo KOtten RYasuura H(1997)Interconnect design for deep submicron ICsProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266534(478-485)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266534
Lefebvre MMarple DSechen CYoffa EDe Micheli GRabaey J(1997)The future of custom cell generation in physical synthesisProceedings of the 34th annual Design Automation Conference10.1145/266021.266196(446-451)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266196
Croix JWong DYoffa EDe Micheli GRabaey J(1997)A fast and accurate technique to optimize characterization tables for logic synthesisProceedings of the 34th annual Design Automation Conference10.1145/266021.266132(337-340)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266132
Croix JWong D(1997)A Fast And Accurate Technique To Optimize Characterization Tables For Logic SynthesisProceedings of the 34th Design Automation Conference10.1109/DAC.1997.597169(337-340)Online publication date: 1997
https://doi.org/10.1109/DAC.1997.597169
Cong JKoh CLeung KHorowitz MRabaey JBarton BPedram M(1996)Simultaneous buffer and wire sizing for performance and power optimizationProceedings of the 1996 international symposium on Low power electronics and design10.5555/252493.252617(271-276)Online publication date: 12-Aug-1996
https://dl.acm.org/doi/10.5555/252493.252617
Tianxiong Xue Kuh EQingjian Yu (1996)A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologiesProceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)10.1109/MCMC.1996.510780(117-122)Online publication date: 1996
https://doi.org/10.1109/MCMC.1996.510780
Cong JHe LRudell R(1995)Optimal wiresizing for interconnects with multiple sourcesProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225116(568-574)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225116
Menezes NBaldick RPileggi LRudell R(1995)A sequential quadratic programming approach to concurrent gate and wire sizingProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.224873(144-151)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.224873
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Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory

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Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory

Gate sizing: finFETs vs 32nm bulk MOSFETs

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

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