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A zero-overhead IC identification technique using clock sweeping and path delay analysis

Authors:

Nicholas Tuzzio,

Kan Xiao,

Xuehui Zhang,

Mohammad TehranipoorAuthors Info & Claims

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

Pages 95 - 98

https://doi.org/10.1145/2206781.2206806

Published: 03 May 2012 Publication History

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Abstract

The counterfeiting of integrated circuits (ICs) has become a major issue for the electronics industry. Counterfeit ICs that find their way into the supply chains of critical applications can have a major impact on the security and reliability of those systems. This paper presents a new method for uniquely identifying ICs through path delay analysis. There is no overhead in terms of area, timing, or power for this method, since it extracts the intrinsic path delay variation information of the IC. Simulation results from 90nm technology and experimental results from 90nm FPGAs demonstrate the effectiveness of our technique.

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Cited By

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Miketic ISalman E(2024)PowerID: Using Supply-Side Impedances of Power Delivery Networks as Signatures for Consumer ElectronicsIEEE Transactions on Consumer Electronics10.1109/TCE.2023.333766870:1(378-388)Online publication date: Feb-2024
https://doi.org/10.1109/TCE.2023.3337668
Gubbi KSaber Latibari BSrikanth ASheaves TBeheshti-Shirazi SPD SRafatirad SSasan AHomayoun HSalehi S(2023)Hardware Trojan Detection Using Machine Learning: A TutorialACM Transactions on Embedded Computing Systems10.1145/357982322:3(1-26)Online publication date: 18-Jan-2023
https://dl.acm.org/doi/10.1145/3579823
Muttaki MPundir NTehranipoor MFarahmandi F(2020)Security Assessment of High-Level SynthesisEmerging Topics in Hardware Security10.1007/978-3-030-64448-2_6(147-170)Online publication date: 10-Nov-2020
https://doi.org/10.1007/978-3-030-64448-2_6
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Index Terms

A zero-overhead IC identification technique using clock sweeping and path delay analysis
1. Hardware
  1. Integrated circuits

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Published In

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

May 2012

388 pages

ISBN:9781450312448

DOI:10.1145/2206781

General Chairs:
Erik Brunvard
University of Utah, USA
,
Ken Stevens
University of Utah, USA
,
Program Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Institute, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 May 2012

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GLSVLSI '12

Sponsor:

SIGDA

GLSVLSI '12: Great Lakes Symposium on VLSI 2012

May 3 - 4, 2012

Utah, Salt Lake City, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Miketic ISalman E(2024)PowerID: Using Supply-Side Impedances of Power Delivery Networks as Signatures for Consumer ElectronicsIEEE Transactions on Consumer Electronics10.1109/TCE.2023.333766870:1(378-388)Online publication date: Feb-2024
https://doi.org/10.1109/TCE.2023.3337668
Gubbi KSaber Latibari BSrikanth ASheaves TBeheshti-Shirazi SPD SRafatirad SSasan AHomayoun HSalehi S(2023)Hardware Trojan Detection Using Machine Learning: A TutorialACM Transactions on Embedded Computing Systems10.1145/357982322:3(1-26)Online publication date: 18-Jan-2023
https://dl.acm.org/doi/10.1145/3579823
Muttaki MPundir NTehranipoor MFarahmandi F(2020)Security Assessment of High-Level SynthesisEmerging Topics in Hardware Security10.1007/978-3-030-64448-2_6(147-170)Online publication date: 10-Nov-2020
https://doi.org/10.1007/978-3-030-64448-2_6
Bhunia STehranipoor M(2019)Electronics Supply ChainHardware Security10.1016/B978-0-12-812477-2.00011-3(141-169)Online publication date: 2019
https://doi.org/10.1016/B978-0-12-812477-2.00011-3
Xiao KForte DTehranipoor M(2016)Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated CircuitsSecure System Design and Trustable Computing10.1007/978-3-319-14971-4_6(211-239)Online publication date: 2016
https://doi.org/10.1007/978-3-319-14971-4_6
Zalivaka SZhang LKlybik VIvaniuk AChang C(2016)Design and Implementation of High-Quality Physical Unclonable Functions for Hardware-Oriented CryptographySecure System Design and Trustable Computing10.1007/978-3-319-14971-4_2(39-81)Online publication date: 2016
https://doi.org/10.1007/978-3-319-14971-4_2
Tehranipoor MGuin UForte DTehranipoor MGuin UForte D(2015)Advanced Detection: Electrical TestsCounterfeit Integrated Circuits10.1007/978-3-319-11824-6_8(157-174)Online publication date: 21-Jan-2015
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Xiao KRahman MForte DHuang YSu MTehranipoor M(2014)Bit selection algorithm suitable for high-volume production of SRAM-PUF2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)10.1109/HST.2014.6855578(101-106)Online publication date: May-2014
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