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Symbolic model checking on SystemC designs

Published: 03 June 2012 Publication History

Abstract

SystemC is a de-facto standard for modeling system-level designs in the early design stage. Verifying SystemC designs is critical in the design process since it can avoid error propagation down to the final implementation. Recent works exploit the software model checking techniques to tackle this important issue. But they abstract away relevant semantic aspects or show limited scalability. In this paper, we devise a symbolic model checking technique using bounded model checking and induction to formally verify SystemC designs. We introduce the notions of behavioral states and transitions to guarantee the soundness of our approach. The experiments show the scalability and the efficiency of our method.

References

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IEEE Standard 1666 SystemC Language Reference Manual, 2005. www.systemc.org.
[2]
C. Helmstetter, F. Maraninchi, L. Maillet-Contoz, and M. Moy, "Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip," In Proc. of FMCAD, 2006.
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S. Kundu, M. Ganai, and R. Gupta, "Partial Order Reduction for Scalable Testing of SystemC TLM Designs," In Proc. of DAC, 2008.
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D. Kroening and N. Sharygina, "Formal Verification of SystemC by Automatic Hardware/Software Partitioning," In Proc. of MEMOCODE, 2005.
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D. Karlsson, P. Eles, and Z. Peng, "Formal Verification of SystemC Designs Using a Petri-Net Based Representation," In Proc. of DATE, 2006.
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P. Herber, J. Fellmuth, and S. Glesner, "Model Checking SystemC Designs using Timed Automata," In Proc. of CODES+ISSS, 2008.
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N. Blanc and D. Kroening, "Race Analysis for SystemC using Model Checking," In Proc. of ICCAD, 2008.
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A. Cimatti, A. Micheli, I. Narasamdya, M. Roveri, "Verifying SystemC: a software model checking approach," In Proc. of FMCAD, 2010.
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A. Cimatti, I. Narasamdya, and M. Roveri, "Boosting Lazy Abstraction for SystemC with Partial Order Reduction," In Proc. of TACAS, 2011.
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C.-N. Chou, C.-H. Hsu, Y.-T. Chao, and C.-Y. Huang, "Formal deadlock checking on high-level SystemC designs," In Proc. of ICCAD, 2010.
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D. Große, H. M. Le, R. Drechsler, "Proving transaction and system-level properties of untimed SystemC TLM designs," In Proc. of MEMOCODE, 2010.
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P. Godefroid, "Model checking for programming languages using VeriSoft," In Proc. of POPL, 1997.
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A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic model checking without BDDs," In Proc. of TACAS, 1999.
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E. Clarke, I. Grumberg, and D. Peled, "Model Checking," The MIT Press, 1999.
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R. Brummayer and A. Biere, "Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays," In Proc. of TACAS, 2009.
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M. Sheeran, S. Singh, and G. Stålmarck, "Checking safety properties using induction and a SAT-Solver," In Proc. of FMCAD, 2000.

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  • (2024)VerificationFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_4(107-152)Online publication date: 26-Mar-2024
  • (2023)Anwendung I: VerifizierungAutomatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme10.1007/978-3-031-36997-1_4(83-112)Online publication date: 20-Sep-2023
  • (2023)Formale Verifikation von SystemC-basierten Entwürfen durch symbolische SimulationVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_4(63-125)Online publication date: 1-Jan-2023
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cover image ACM Conferences
DAC '12: Proceedings of the 49th Annual Design Automation Conference
June 2012
1357 pages
ISBN:9781450311991
DOI:10.1145/2228360
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 03 June 2012

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Author Tags

  1. SystemC
  2. formal verification
  3. symbolic model checking

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  • Research-article

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DAC '12
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DAC '12: The 49th Annual Design Automation Conference 2012
June 3 - 7, 2012
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2024)VerificationFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_4(107-152)Online publication date: 26-Mar-2024
  • (2023)Anwendung I: VerifizierungAutomatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme10.1007/978-3-031-36997-1_4(83-112)Online publication date: 20-Sep-2023
  • (2023)Formale Verifikation von SystemC-basierten Entwürfen durch symbolische SimulationVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_4(63-125)Online publication date: 1-Jan-2023
  • (2022)IntroductionEnhanced Virtual Prototyping for Heterogeneous Systems10.1007/978-3-031-05574-4_1(1-13)Online publication date: 3-May-2022
  • (2021)Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challengesScience China Information Sciences10.1007/s11432-020-3308-465:1Online publication date: 23-Dec-2021
  • (2019)KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design2019 Formal Methods in Computer Aided Design (FMCAD)10.23919/FMCAD.2019.8894295(105-109)Online publication date: Oct-2019
  • (2019)Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663838:7(1359-1372)Online publication date: Jul-2019
  • (2019)Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes2019 22nd Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2019.00081(522-529)Online publication date: Aug-2019
  • (2019)Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems2019 IEEE 28th Asian Test Symposium (ATS)10.1109/ATS47505.2019.00029(159-1595)Online publication date: Dec-2019
  • (2018)SCbenchProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201715(440-445)Online publication date: 22-Jan-2018
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