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On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

Published: 03 June 2012 Publication History

Abstract

In this paper, we investigate the impact of circuit misbehavior due to parametric variations and voltage scaling on the performance of wireless communication systems. Our study reveals the inherent error resilience of such systems and argues that sufficiently reliable operation can be maintained even in the presence of unreliable circuits and manufacturing defects. We further show how selective application of more robust circuit design techniques is sufficient to deal with high defect rates at low overhead and improve energy efficiency with negligible system performance degradation.

References

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J. M. Rabaey, "Low Power Design Essentials", Springer, 2009.
[2]
S. Bhunia, et al, "Low-Power Variation-Tolerant Design in Nanometer Silicon," Springer 2011.
[3]
S. Borkar, et al., "Design and reliability challenges in nanometer technologies," IEEE DAC, pp. 75, 2004.
[4]
A. Shrivastava, et al., "Statistical Analysis and Optimization for VLSI: Timing and Power", Springer, 2005.
[5]
Z. Chishti, et al., "Improving Cache Lifetime Reliability at Ultra-low Voltages," IEEE MICRO, 2009.
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C. Wilkerson, et al., "Trading off Cache Capacity for Reliability to Enable Low Voltage Operation," IEEE ISCA, 2008.
[7]
Shi-Ting Zhou, et al. "Minimizing Total Area of Low-Voltage SRAM Arrays through Joint Optimization of Cell Size, Redundancy, and ECC," IEEE ICCD, 2010.
[8]
Y. Emre, et al., "Memory Error Compensation Techniques for JPEG2000," IEEE SiPS, 2010.
[9]
I. J. Chang, et al., "A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications," IEEE Trans. on CSVT, 2011.
[10]
High speed downlink packet access (HSDPA), Third Generation Partnership Project TS 25.308, Rev. 10.5.0, Jun. 2011.
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S. Mukhopadhyay, "Statistical design and optimization of SRAM cell for yield enhancement", IEEE ICCAD, 2004.
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P. Zuber, et al., "Statistical SRAM analysis for yield enhancement," IEEE DATE, 2011.

Cited By

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  • (2017)Will Chips of the Future Learn How to Feel Pain and Cure Themselves?IEEE Design & Test10.1109/MDAT.2017.273084134:5(80-87)Online publication date: Oct-2017
  • (2017)Retention Time Modeling: The Key to Low-Power GC-eDRAMsGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_3(27-48)Online publication date: 7-Jul-2017
  • (2017)Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior ArtGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_2(13-26)Online publication date: 7-Jul-2017
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  1. On the exploitation of the inherent error resilience of wireless systems under unreliable silicon

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    cover image ACM Conferences
    DAC '12: Proceedings of the 49th Annual Design Automation Conference
    June 2012
    1357 pages
    ISBN:9781450311991
    DOI:10.1145/2228360
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 03 June 2012

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    Author Tags

    1. energy-efficiency
    2. error-resiliency
    3. memory failures
    4. reliability
    5. wireless communication systems
    6. yield

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    DAC '12
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    DAC '12: The 49th Annual Design Automation Conference 2012
    June 3 - 7, 2012
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2017)Will Chips of the Future Learn How to Feel Pain and Cure Themselves?IEEE Design & Test10.1109/MDAT.2017.273084134:5(80-87)Online publication date: Oct-2017
    • (2017)Retention Time Modeling: The Key to Low-Power GC-eDRAMsGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_3(27-48)Online publication date: 7-Jul-2017
    • (2017)Gain-Cell eDRAMs (GC-eDRAMs): Review of Basics and Prior ArtGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_2(13-26)Online publication date: 7-Jul-2017
    • (2017)Embedded Memories: IntroductionGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip10.1007/978-3-319-60402-2_1(1-12)Online publication date: 7-Jul-2017
    • (2016)Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.251270663:2(222-232)Online publication date: Feb-2016
    • (2015)Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memoriesProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755864(489-494)Online publication date: 9-Mar-2015
    • (2015)Mitigating the impact of faults in unreliable memories for error-resilient applicationsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744871(1-6)Online publication date: 7-Jun-2015
    • (2014)Improved fault tolerance of Turbo decoding based on optimized index assignmentsAdvances in Radio Science10.5194/ars-12-187-201412(187-195)Online publication date: 10-Nov-2014
    • (2014)Polynomial Sufficient Conditions of Well-Behavedness and Home Markings in Subclasses of Weighted Petri NetsACM Transactions on Embedded Computing Systems10.1145/262734913:4s(1-25)Online publication date: 28-Jul-2014
    • (2014)Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming NetworksACM Transactions on Embedded Computing Systems10.1145/258466813:4s(1-25)Online publication date: 1-Apr-2014
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