research-article

X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug

Authors:

Qiang XuAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 555 - 560

https://doi.org/10.1145/2228360.2228460

Published: 03 June 2012 Publication History

Abstract

The effectiveness of at-speed silicon debug is constrained by the limited trace buffer size and/or trace port bandwidth, requiring highly-efficient trace data compression solutions. As it is usually inevitable to have unknown 'X' values during silicon debug, trace compressor should be equipped with X-tolerance feature in order not to significantly degrade error detection capability. To tackle this problem, this paper presents a novel reconfigurable X-tolerant trace compressor, namely X-Tracer, which is able to tolerate as many X-bits as possible in the trace streams while guaranteeing high compression ratio, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.

References

[1]

M. Abramovici. In-System Silicon Validation and Debug. IEEE Design & Test of Computers, 25(3):216--223, May-June 2008.

Digital Library

[2]

Semiconductor Industry Association (SIA). The International Technology Roadmap for Semiconductors (ITRS): 2003 Edition. http://public.itrs.net/Files/2003ITRS/Home2003.htm, 2003.

[3]

X. Liu and Q. Xu, "On signal tracing in post-silicon validation," in Proceedings IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 262--267, 2010.

Digital Library

[4]

ARM Ltd. How CoreSight Technology Gets Higher Performance, More Reliable Product to Market Quicker. http://www.arm.com.

[5]

R. Leatherman and N. Stollon. An Embedded Debugging Architecture for SOCs. IEEE Potentials, Feb.-Mar. 2005.

[6]

X. Liu and Q. Xu. Interconnection fabric design for tracing signals in post-silicon validation. In Proc. ACM/IEEE Design Automation Conference (DAC), pp. 352--357, 2009.

Digital Library

[7]

R. H. Livengood and D. Medeiros. Design for (Physical) Debug for Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits. In Proc. IEEE International Test Conference (ITC), pp. 877--882, 2007.

Digital Library

[8]

K. H. Chang, I. L. Markov, and V. Bertacco. Fixing Design Errors with Counterexamples and Resynthesis. In Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 944--949, 2007.

Digital Library

[9]

S. Tang and Q. Xu, "A multi-core debug platform for NoC-based systems," in Proceedings IEEE/ACM Design, Automation, and Test in Europe (DATE), 2008, pp. 870--875.

Digital Library

[10]

H. F. Ko and N. Nicolici. Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation. In Proc. Design, Automation, and Test in Europe (DATE), pp. 1298--1303, 2008.

Digital Library

[11]

X. Liu and Q. Xu. Trace signal selection for visibility enhancement in post-silicon validation. In Proceedings Design, Automation, and Test in Europe (DATE), pp. 1338--1343, 2009.

Digital Library

[12]

J.-S. Yang and N. A. Touba. Automated Selection of Signals to Observe for Efficient Silicon Debug. In Proc. IEEE VLSI Test Symposium (VTS), pp. 79--84, 2009.

Digital Library

[13]

X. Liu and Q. Xu, "On Multiplexed Signal Tracing for Post-Silicon Debug," in Proceedings IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1--6, 2011.

[14]

S. B. Park and S. Mitra. IFRA: Instruction footprint recording and analysis for post-silicon bug localization in processors. In Proc. ACM/IEEE Design Automation Conference (DAC), pp. 373--378, 2008.

Digital Library

[15]

C. H. Lai, et al. A trace-capable instruction cache for cost efficient real-time program trace compression in SoC. In Proc. ACM/IEEE Design Automation Conference (DAC), pp. 136--141, 2009.

Digital Library

[16]

A. Vishnoi, P. R. Panda, and M. Balakrishnan. Cache Aware Compression for Processor Debug Suppport. In Proc. Design, Automation, and Test in Europe (DATE), 2009.

Digital Library

[17]

E. Anis and N. Nicolici. On Using Lossless Compresstion of Debug Data in Embedded Logic Analysis. In Proc. IEEE International Test Conference (ITC), pp. 1--10, October 2007.

[18]

S. Prabhakar, R. Sethuram, and M. S. Hsiao. Trace Buffer-Based Silicon Debug with Lossless Compression. In Proc. International Conference on VLSI Design, pp. 358--363, 2011.

Digital Library

[19]

J.-S. Yang and N. A. Touba. Enhancing Silicon Debug via Periodic Monitoring. In Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 125--133, 2008.

Digital Library

[20]

E. Anis and N. Nicolici. Low cost debug architecture using lossy compression for silicon debug. In Proc. Design, Automation, and Test in Europe (DATE), pp. 225--230, 2007.

Digital Library

[21]

J. S. Yang and N. A. Touba. Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. In Proc. IEEE VLSI Test Symposium (VTS), pp. 345--351, 2008.

Digital Library

[22]

M. C.-T. Chao, et al. Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Compaction. In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 80--87, 2005.

Digital Library

[23]

S. Mitra, M. Mitzenmacher, S. S. Lumetta, and N. Patil. X-Tolerant Test Response Compaction. IEEE Design & Test of Computers, 22(6):566--574, 2005.

Digital Library

[24]

J. S. Yang, N. A. Touba, S. Y. Yang, and T. M. Mak. Industrial Case Study for X-Canceling MISR. In Proc. IEEE International Test Conference (ITC), 2009.

[25]

N. A. Touba. X-Canceling MISR-An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR. In Proc. IEEE International Test Conference (ITC), pp. 1--10, 2007.

Cited By

Suresh CSinanoglu OOzev S(2016)Adapting to Varying Distribution of Unknown Response BitsACM Transactions on Design Automation of Electronic Systems10.1145/283548921:2(1-22)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2835489
Deutsch SChakrabarty K(2014)Massive signal tracing using on-chip DRAM for in-system silicon debug2014 International Test Conference10.1109/TEST.2014.7035363(1-10)Online publication date: Oct-2014
https://doi.org/10.1109/TEST.2014.7035363

Recommendations

Silicon debug of a co-processor array for video applications
HLDVT '00: Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)

For today's multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of ...
Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug
ATS '09: Proceedings of the 2009 Asian Test Symposium

An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace ...
A reconfigurable design-for-debug infrastructure for SoCs
DAC '06: Proceedings of the 43rd annual Design Automation Conference

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Conference

DAC '12

Sponsor:

EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
185
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Suresh CSinanoglu OOzev S(2016)Adapting to Varying Distribution of Unknown Response BitsACM Transactions on Design Automation of Electronic Systems10.1145/283548921:2(1-22)Online publication date: 28-Jan-2016
https://dl.acm.org/doi/10.1145/2835489
Deutsch SChakrabarty K(2014)Massive signal tracing using on-chip DRAM for in-system silicon debug2014 International Test Conference10.1109/TEST.2014.7035363(1-10)Online publication date: Oct-2014
https://doi.org/10.1109/TEST.2014.7035363

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents