research-article

Assessing the performance limits of parallelized near-threshold computing

Authors:

Nathaniel Pinckney,

Ronald G. Dreslinski,

Dennis Sylvester,

David BlaauwAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1147 - 1152

https://doi.org/10.1145/2228360.2228571

Published: 03 June 2012 Publication History

Abstract

Supply voltage scaling has stagnated in recent technology nodes, leading to so-called "dark silicon." In this paper, we investigate the limit of voltage scaling together with task parallelization to maintain task completion latency. When accounting for parallelization overheads, minimum task energy is obtained at "near threshold" supply-voltages across 6 commercial technology nodes and provides 4X improvement in overall CMP performance.

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Cited By

Moon SChandrarathna SShafique ALee J(2024)A Compact DC-DC Converter With Pulse-Counting MPPT and Fast One-Path Self-Startup for Thermal Energy HarvestingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.337700371:5(2457-2470)Online publication date: May-2024
https://doi.org/10.1109/TCSI.2024.3377003
Vangal SPaul SHsu SAgarwal AKumar SKrishnamurthy RKrishnamurthy HTschanz JDe VKim C(2021)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and OpportunitiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306164929:5(843-856)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1109/TVLSI.2021.3061649
Knag PChen GSumbul HKumar RHsu SAgarwal AKar MKim SAnders MKaul HKrishnamurthy R(2021)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.303861656:4(1082-1092)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3038616
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Index Terms

Assessing the performance limits of parallelized near-threshold computing
1. Hardware
  1. Robustness

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Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Moon SChandrarathna SShafique ALee J(2024)A Compact DC-DC Converter With Pulse-Counting MPPT and Fast One-Path Self-Startup for Thermal Energy HarvestingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.337700371:5(2457-2470)Online publication date: May-2024
https://doi.org/10.1109/TCSI.2024.3377003
Vangal SPaul SHsu SAgarwal AKumar SKrishnamurthy RKrishnamurthy HTschanz JDe VKim C(2021)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and OpportunitiesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306164929:5(843-856)Online publication date: 1-May-2021
https://dl.acm.org/doi/10.1109/TVLSI.2021.3061649
Knag PChen GSumbul HKumar RHsu SAgarwal AKar MKim SAnders MKaul HKrishnamurthy R(2021)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.303861656:4(1082-1092)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3038616
Hung CWang SHung CWang S(2021)Low-Power and Low-Voltage VLSI Circuit Design Techniques for Biomedical ApplicationsUltra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-to-Digital Converter for Biomedical Applications10.1007/978-3-030-88845-9_2(23-54)Online publication date: 8-Dec-2021
https://doi.org/10.1007/978-3-030-88845-9_2
Pandey PGundi NBasu PShabanian TPatrick MChakraborty KRoy S(2020)Challenges and Opportunities in Near-Threshold DNN Accelerators around Timing ErrorsJournal of Low Power Electronics and Applications10.3390/jlpea1004003310:4(33)Online publication date: 16-Oct-2020
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Vangal SPaul SHsu SAgarwal AKrishnamurthy RTschanz JDe V(2020)Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-ChipsJournal of Low Power Electronics and Applications10.3390/jlpea1002001610:2(16)Online publication date: 14-May-2020
https://doi.org/10.3390/jlpea10020016
Pagani SManoj PJantsch AHenkel J(2020)Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A SurveyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287816839:1(101-116)Online publication date: Jan-2020
https://doi.org/10.1109/TCAD.2018.2878168
Wang JFu XWang XLiu SGao LZhang W(2020)Enabling Energy-Efficient and Reliable Neural Network via Neuron-Level Voltage ScalingIEEE Transactions on Computers10.1109/TC.2020.297315069:10(1460-1473)Online publication date: 1-Oct-2020
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Salamin SAmrouch HHenkel J(2019)Selecting the Optimal Energy Point in Near-Threshold Computing2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715211(1691-1696)Online publication date: Mar-2019
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Bal ASaha SRoy SChakraborty K(2018)Dynamic Choke Sensing for Timing Error Resilience in NTC SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275296326:1(1-10)Online publication date: Jan-2018
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