research-article

Chisel: constructing hardware in a Scala embedded language

Authors:

Huy Vo,

Krste AsanovićAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1216 - 1225

https://doi.org/10.1145/2228360.2228584

Published: 03 June 2012 Publication History

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Abstract

In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. By embedding Chisel in the Scala programming language, we raise the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to map to either FPGAs or to a standard ASIC flow for synthesis. This paper presents Chisel, its embedding in Scala, hardware examples, and results for C++ simulation, Verilog emulation and ASIC synthesis.

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https://doi.org/10.1109/TVLSI.2024.3496858
Fang WLu YLiu SZhang QXu CWu Wills LZhang HXie Z(2025)Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342090444:1(200-213)Online publication date: Jan-2025
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Index Terms

Chisel: constructing hardware in a Scala embedded language
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
    2. High-level and register-transfer level synthesis

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Published In

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

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Published: 03 June 2012

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DAC '12: The 49th Annual Design Automation Conference 2012

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https://doi.org/10.1109/TVLSI.2024.3496858
Fang WLu YLiu SZhang QXu CWu Wills LZhang HXie Z(2025)Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation TechniquesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342090444:1(200-213)Online publication date: Jan-2025
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Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)

Application-Specific FPGA using heterogeneous logic blocks

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Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)

Application-Specific FPGA using heterogeneous logic blocks

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