Cited By
View all- Beerel PBurch JMeng T(1998)Checking Combinational Equivalence of Speed-Independent CircuitsFormal Methods in System Design10.1023/A:100866660543713:1(37-85)Online publication date: 1-May-1998
This paper develops a theoretical framework for the hazard-free gate-level implementation of speed-independent circuits specified by event-based models, such as signal transition graphs (for processes with AND causality and input choice) or their ...
Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in the design library. The proposed ...
We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a golden hazard-free circuit C_1 and a target circuit C_2 that can be derived from C_1 through only combinational decomposition and ...
Association for Computing Machinery
New York, NY, United States
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in