Article

Free access

Area-speed tradeoffs for hierarchical field-programmable gate arrays

Authors:

Vi Cuong Chan,

David M. LewisAuthors Info & Claims

FPGA '96: Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Pages 51 - 57

https://doi.org/10.1145/228370.228378

Published: 15 February 1996 Publication History

PDF eReader

Abstract

No abstract available.

References

[1]

Aditya A. Aggarwal, "Routing Architectures for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1994.

Google Scholar

[2]

ISCAS '85 Test Generation Benchmark Data obtained from the Microelectronics Centre of North Carolina (MCNC)

Google Scholar

[3]

S. Brown, R. J. Francis, J. Rose and Z. G. Vranesic, Field- Programmable Gate Arrays, Kluwer Academic Publishers, 1992.

Digital Library

Google Scholar

[4]

S. Singh, J. Rose, D. Lewis, K. Chung and P. Chow, "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed", Proceedings of the 1991 Custom Integrated Circuits Conference (CICC-91), May 1991, pp. 6.1.1-6.1.6.

Crossref

Google Scholar

[5]

J. Rose, R. J. Francis, D. Lewis, P. Chow, "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency", IEEE Journal of Solid State Circuits (JSSC), Vol. 25, No. 5, Oct. 1990, pp. 1217-1225.

Crossref

Google Scholar

[6]

S. Singh, "The Effect of Logic Block Architecture on FPGA Performance", M.A.Sc. Thesis, Department of Electrical Engineering, University of Toronto, 1991.

Google Scholar

[7]

K. Chung, S. Singh, J. Rose and P. Chow, "Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays", Proceedings of the First International Workshop on Field Programmable Logic and Applications, Oxford, Sept. 1991, pp. 103-113.

Google Scholar

[8]

J. Rose and S. Brown, "Flexibility of Interconnection Structures in Field Programmable Gate Arrays", IEEE Journal of Solid State Circuits (JSSC), Vol. 26, No. 3, March 1991, pp. 277-282.

Crossref

Google Scholar

[9]

S.D. Brown, "Routing Algorithms and Architectures for Field Programmable Gate Arrays", PhD. Thesis, University of Toronto, 1992.

Digital Library

Google Scholar

[10]

The Programmable Logic Data Book, Xilinx Inc., 1994.

Google Scholar

[11]

Vi C. Chan, "Timing Optimization for Hierarchical FPGAs", M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 1995.

Google Scholar

[12]

R. Brayton, R. Rudell, A. Sangiovanni Vincentelli and A. Wang, "MIS: a Multiple-Level Logic Optimization System", IEEE Transactions on CAD (TCAD), Vol CAD-6, No. 6, Nov. 1987, pp. 1062-1081.

Digital Library

Google Scholar

[13]

R. J. Francis, J. Rose and Z. Vranesic, "Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs", Proceedings of the 28th Design Automation Conference (DAC-28), June 1991, pp. 227-233.

Digital Library

Google Scholar

[14]

J. Rose, Z. Vranesic and W. M. Snelgrove, "ALTOR: An automatic standard cell layout program", in Proceeding of the Canadian Conference on VLSI, Nov. 1985, pp. 168-173.

Google Scholar

[15]

Fiduccia, C.M., and Mattheyses, R.M., "A linear-time Heuristics for Improving Network Partitions", Proceedings of the 19th Design Automation Conference (DAC- 19), 1982, pp. 175-181.

Digital Library

Google Scholar

[16]

B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Tech. Journal, 49, 2, 1970, pp. 291-308.

Google Scholar

[17]

Wilm E. Donath, Reini, J. Norman, Bhuwan K. Agrawal, et. al, "Timing Driven Placement Using Complete Path Delays", 27th ACM/IEEE Design Automation Conference, 1990, pp. 84-89.

Digital Library

Google Scholar

[18]

P. S. Hauge, R. Nair and E. J. Yoffa, "Circuit Placement for Predictable Performance", IEEE Proc. of ICCAD, 1987, pp. 88-91.

Google Scholar

[19]

Michael Burstein, Mary N. Youssef, "Timing Influenced Layout Design", 22nd Design Automation Conference, 1985, pp. 124-130.

Digital Library

Google Scholar

[20]

Grant A. Cheston, "Incremental Algorithms in Graph Theory", Ph.D. Thesis, Department of Computer Science, University of Toronto, 1976.

Digital Library

Google Scholar

[21]

Altera Corp., "Flex 8000 Handbook", 1994

Google Scholar

Cited By

View all

Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Field Programmable Gate Arrays: An OverviewThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_3(43-71)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_3
Dai ZBanerji D(2003)Routability Prediction for Field Programmable Gate Arrays with a Routing HierarchyProceedings of the 16th International Conference on VLSI Design10.5555/832285.835602Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835602
Zhibin Dai Banerji D(2003)Routability prediction for Field Programmable Gate Arrays with a routing hierarchy16th International Conference on VLSI Design, 2003. Proceedings.10.1109/ICVD.2003.1183119(85-90)Online publication date: 2003
https://doi.org/10.1109/ICVD.2003.1183119
Show More Cited By

Index Terms

Area-speed tradeoffs for hierarchical field-programmable gate arrays
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

Recommendations

FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

We use a fully timing-driven experimental flow [4] [15] in which a set of benchmark circuits are synthesized into different cluster-based [2] [3] [15] logic block architectures, which contain groups of LUTs and flip-flops. We look across all ...
Automatic generation of FPGA routing architectures from high-level descriptions
FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

In this paper we present a “high-level” FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. We then present an “architecture generator” built into the VPR CAD tool [1, 2] that ...

Comments

Information & Contributors

Information

Published In

FPGA '96: Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

February 1996

158 pages

ISBN:0897917731

DOI:10.1145/228370

Chairmen:
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada
,
Carl Ebeling
Univ. of Washington, Seattle

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1996

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPGA96

Sponsor:

SIGDA

FPGA96: 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 11 - 13, 1996

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

6
Total Citations
View Citations
343
Total Downloads

Downloads (Last 12 months)28
Downloads (Last 6 weeks)11

Reflects downloads up to 16 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Field Programmable Gate Arrays: An OverviewThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_3(43-71)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_3
Dai ZBanerji D(2003)Routability Prediction for Field Programmable Gate Arrays with a Routing HierarchyProceedings of the 16th International Conference on VLSI Design10.5555/832285.835602Online publication date: 4-Jan-2003
https://dl.acm.org/doi/10.5555/832285.835602
Zhibin Dai Banerji D(2003)Routability prediction for Field Programmable Gate Arrays with a routing hierarchy16th International Conference on VLSI Design, 2003. Proceedings.10.1109/ICVD.2003.1183119(85-90)Online publication date: 2003
https://doi.org/10.1109/ICVD.2003.1183119
Jiaofeng Pan Yu-Liang Wu Wong C(1998)On the optimal sub-routing structures of 2-D FPGA greedy routing architecturesProceedings of 1998 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1998.669544(535-540)Online publication date: 1998
https://doi.org/10.1109/ASPDAC.1998.669544
Pan JWu YWong CYan G(1998)On the optimal four-way switch box routing structures of FPGA greedy routing architecturesIntegration, the VLSI Journal10.1016/S0167-9260(98)00011-X25:2(137-159)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1016/S0167-9260%2898%2900011-X
Yu-Liang Wu Chang DMarek-Sadowska MTsukiyama S(1997)Not necessarily more switches more routability [sic.]Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference10.1109/ASPDAC.1997.600339(579-584)Online publication date: 1997
https://doi.org/10.1109/ASPDAC.1997.600339

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

FPGA routing architecture: segmentation and buffering to optimize speed and density

The effect of LUT and cluster size on deep-submicron FPGA performance and density

Automatic generation of FPGA routing architectures from high-level descriptions