Industry focus session on low-power design

Low-power EDA has come a long way in from its infancy almost 20 years ago, when the first low power tools for logic synthesis were introduced. Currently a large number of power-aware tools provide a spectrum of capabilities to address power issues, from ...

System on Chip interconnects require first-in first-out buffers (FIFOs) to handle different data rates between IP cores. The design of an interconnect channel containing multiple stages of FIFO require making tradeoff between throughput and power ...

Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication ...