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Acceleration of bulk memory operations in a heterogeneous multicore architecture

Published: 19 September 2012 Publication History

Abstract

In this paper, we present a novel approach of using the integrated GPU to accelerate conventional operations that are normally performed by the CPUs, the bulk memory operations, such as memcpy or memset. Offloading the bulk memory operations to the GPU has many advantages, i) the throughput driven GPU outperforms the CPU on the bulk memory operations; ii) for on-die GPU with unified cache between the GPU and the CPU, the GPU private caches can be leveraged by the CPU for storing moved data and reducing the CPU cache bottleneck; iii) with additional lightweight hardware, asynchronous offload can be supported as well; and iv) different from the prior arts using dedicated hardware copy engines (e.g., DMA), our approach leverages the exiting GPU hardware resources as much as possible. The performance results based on our solution showed that offloaded bulk memory operations outperform CPU up to 4.3 times in micro benchmarks while still using less resources. Using eight real world applications and a cycle based full system simulation environment, the results showed 30% speedup for five, more than 20% speedup for two of the eight applications.

References

[1]
Fes2: A full-system execution-driven simulator for x86. http://fes2.cs.uiuc.edu/index.html, 2007.
[2]
Magnusson, P., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., and Werner, B. Simics: A full system simulation platform. Computer 35, 2 (Feb 2002), 50--58.
[3]
Meng, J., and Skadron, K. Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling. In Proceedings of the 2009 IEEE international conference on Computer design (Piscataway, NJ, USA, 2009), ICCD'09, IEEE Press, pp. 282--288.

Cited By

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  • (2021)HAVS: Hardware-accelerated Shared-memory-based VPP Network StackIEEE INFOCOM 2021 - IEEE Conference on Computer Communications10.1109/INFOCOM42981.2021.9488808(1-10)Online publication date: 10-May-2021
  • (2018)Accelerated bulk memory operations on heterogeneous multi-core systemsThe Journal of Supercomputing10.1007/s11227-018-2589-x74:12(6898-6922)Online publication date: 1-Dec-2018

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  1. Acceleration of bulk memory operations in a heterogeneous multicore architecture

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    cover image ACM Conferences
    PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques
    September 2012
    512 pages
    ISBN:9781450311823
    DOI:10.1145/2370816

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 19 September 2012

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    Author Tags

    1. bulk memory operation
    2. gpu
    3. heterogeneous multicore architecture
    4. simd

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    PACT '12
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    • IFIP WG 10.3
    • SIGARCH
    • IEEE CS TCPP
    • IEEE CS TCAA

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    Overall Acceptance Rate 121 of 471 submissions, 26%

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    • (2021)HAVS: Hardware-accelerated Shared-memory-based VPP Network StackIEEE INFOCOM 2021 - IEEE Conference on Computer Communications10.1109/INFOCOM42981.2021.9488808(1-10)Online publication date: 10-May-2021
    • (2018)Accelerated bulk memory operations on heterogeneous multi-core systemsThe Journal of Supercomputing10.1007/s11227-018-2589-x74:12(6898-6922)Online publication date: 1-Dec-2018

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