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Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing

Published: 19 September 2012 Publication History

Abstract

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References

[1]
AMD R700-Family Instruction Set Architecture Reference Guide, February 2011.
[2]
S. McFarling, Combining branch predictors, Digital Western Research Lab (WRL) Technical Report, 1993.
[3]
NVIDIA CUDA Programming Guide 4.1, 2011

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  1. Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing

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    Published In

    cover image ACM Conferences
    PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques
    September 2012
    512 pages
    ISBN:9781450311823
    DOI:10.1145/2370816

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 19 September 2012

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    Author Tags

    1. energy
    2. gpgpu
    3. heterogeneous
    4. ilp

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    PACT '12
    Sponsor:
    • IFIP WG 10.3
    • SIGARCH
    • IEEE CS TCPP
    • IEEE CS TCAA

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    Overall Acceptance Rate 121 of 471 submissions, 26%

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    • (2024)SIMILMicroprocessors & Microsystems10.1016/j.micpro.2024.105105111:COnline publication date: 1-Nov-2024
    • (2017)RGCA: A Reliable GPU Cluster Architecture for Large-Scale Internet of Things Computing Based on Effective Performance-Energy OptimizationSensors10.3390/s1708179917:8(1799)Online publication date: 4-Aug-2017
    • (2016)Virtual threadACM SIGARCH Computer Architecture News10.1145/3007787.300120144:3(609-621)Online publication date: 18-Jun-2016
    • (2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016
    • (2016)Virtual threadProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.59(609-621)Online publication date: 18-Jun-2016
    • (2013)ARGOProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555722(1-9)Online publication date: 29-Sep-2013
    • (2013)ARGO: Aging-aware GPGPU register file allocation2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODES-ISSS.2013.6659017(1-9)Online publication date: Sep-2013

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