Fang YChen QXiong NZhao DWang J(2017)RGCA: A Reliable GPU Cluster Architecture for Large-Scale Internet of Things Computing Based on Effective Performance-Energy OptimizationSensors10.3390/s1708179917:8(1799)Online publication date: 4-Aug-2017
https://doi.org/10.3390/s17081799
Yoon MKim KLee SRo WAnnavaram M(2016)Virtual threadACM SIGARCH Computer Architecture News10.1145/3007787.300120144:3(609-621)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001201
Middendorf LHaubelt C(2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016
https://doi.org/10.1109/MCSoC.2016.26
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Index Terms

Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Published In

PACT '12: Proceedings of the 21st international conference on Parallel architectures and compilation techniques

September 2012

512 pages

ISBN:9781450311823

DOI:10.1145/2370816

General Chairs:
Pen-Chung Yew
University of Minnesota
,
Sangyeun Cho
University of Pittsburgh
,
Program Chairs:
Luiz DeRose
Cray, Inc.
,
David J. Lilja
University of Minnesota

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 September 2012

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Conference

PACT '12

Sponsor:

IFIP WG 10.3
SIGARCH
IEEE CS TCPP
IEEE CS TCAA

PACT '12: International Conference on Parallel Architectures and Compilation Techniques

September 19 - 23, 2012

Minnesota, Minneapolis, USA

Acceptance Rates

Overall Acceptance Rate 121 of 471 submissions, 26%

Upcoming Conference

PACT '24

Sponsor:
sigarch

International Conference on Parallel Architectures and Compilation Techniques

October 14 - 16, 2024

Long Beach , CA , USA

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Fang YChen QXiong NZhao DWang J(2017)RGCA: A Reliable GPU Cluster Architecture for Large-Scale Internet of Things Computing Based on Effective Performance-Energy OptimizationSensors10.3390/s1708179917:8(1799)Online publication date: 4-Aug-2017
https://doi.org/10.3390/s17081799
Yoon MKim KLee SRo WAnnavaram M(2016)Virtual threadACM SIGARCH Computer Architecture News10.1145/3007787.300120144:3(609-621)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1145/3007787.3001201
Middendorf LHaubelt C(2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016
https://doi.org/10.1109/MCSoC.2016.26
Yoon MKim KLee SRo WAnnavaram MMin SLoh G(2016)Virtual threadProceedings of the 43rd International Symposium on Computer Architecture10.1109/ISCA.2016.59(609-621)Online publication date: 18-Jun-2016
https://dl.acm.org/doi/10.1109/ISCA.2016.59
Namaki-Shoushtari MRahimi ADutt NGupta PGupta RMarculescu RPanda P(2013)ARGOProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555722(1-9)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555692.2555722
Namaki-Shoushtari MRahimi ADutt NGupta PGupta R(2013)ARGO: Aging-aware GPGPU register file allocation2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODES-ISSS.2013.6659017(1-9)Online publication date: Sep-2013
https://doi.org/10.1109/CODES-ISSS.2013.6659017

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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading

Revisiting ILP designs for throughput-oriented GPGPU architecture

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