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Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs

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Ulf SchlichtmannAuthors Info & Claims

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 181 - 186

https://doi.org/10.1145/2380445.2380477

Published: 07 October 2012 Publication History

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Abstract

This work proposes a flexible and modular solution for nonintrusive tracing and debugging of software on embedded SoC platforms. It utilizes a separate, dedicated Network-on-Chip (NoC) interconnect with a hierarchical unidirectional ring topology to connect a multitude of monitoring devices. The devices are controlled via a debugger attached to the NoC. They use the network to receive control information and send back observations, which the debugger uses to construct a trace. The system utilizes a very accurate and efficient differential timestamping approach. It allows working with multi-synchronous SoCs, identifying concurrencies and other temporal properties in the SoC and coping with partial power downs and clock gatings. The proposed solution requires a low amount of hardware resources and at the same time provides unmatched capabilities.

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Cited By

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Dehbashi MFey G(2015)Transaction-based online debug for NoC-based multiprocessor SoCsMicroprocessors & Microsystems10.1016/j.micpro.2015.03.00339:3(157-166)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.03.003
Dehbashi MFey GDehbashi MFey G(2014)Online Debug for NoC-Based Multiprocessor SoCsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_9(133-157)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_9
Dehbashi MFey GDehbashi MFey G(2014)Efficient Automated Speedpath DebuggingDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_8(115-129)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_8
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Index Terms

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
1. Hardware
  1. Integrated circuits
    1. Interconnect
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Software defect analysis
        Software testing and debugging

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Published In

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2012

596 pages

ISBN:9781450314268

DOI:10.1145/2380445

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Naehyuck Chang
Seoul National University, Korea
,
Franco Fummi
University of Verona, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 October 2012

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Conference

ESWEEK'12

Sponsor:

ESWEEK'12: Eighth Embedded System Week

October 7 - 12, 2012

Tampere, Finland

Acceptance Rates

CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

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Dehbashi MFey G(2015)Transaction-based online debug for NoC-based multiprocessor SoCsMicroprocessors & Microsystems10.1016/j.micpro.2015.03.00339:3(157-166)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.03.003
Dehbashi MFey GDehbashi MFey G(2014)Online Debug for NoC-Based Multiprocessor SoCsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_9(133-157)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_9
Dehbashi MFey GDehbashi MFey G(2014)Efficient Automated Speedpath DebuggingDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_8(115-129)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_8
Dehbashi MFey GDehbashi MFey G(2014)Automated Debugging for Timing VariationsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_7(101-114)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_7
Dehbashi MFey GDehbashi MFey G(2014)Analyzing Timing VariationsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_6(79-99)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_6
Dehbashi MFey GDehbashi MFey G(2014)Automated Debugging for Synchronization BugsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_5(63-76)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_5
Dehbashi MFey GDehbashi MFey G(2014)Automated Debugging from Pre-Silicon to Post-SiliconDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_4(49-62)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_4
Dehbashi MFey GDehbashi MFey G(2014)Automated Debugging for Logic BugsDebug Automation from Pre-Silicon to Post-Silicon10.1007/978-3-319-09309-3_3(27-48)Online publication date: 3-Sep-2014
https://doi.org/10.1007/978-3-319-09309-3_3

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