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Improving the efficiency of power simulators by input vector compaction

Authors:

Chi-Ying Tsui,

Radu Marculescu,

Diana Marculescu,

Massoud PedramAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

Pages 165 - 168

https://doi.org/10.1145/240518.240549

Published: 01 June 1996 Publication History

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References

[1]

R. Burch, F. Najm, R Yang and T. Trick, "A Monte Carlo approach for power estimation", IEEE Transaction on VLSI Systems, vol. 1, no. 1, pp. 63-71, March,1993

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C-Y. Tsui, M. Pedram and A. M. Despain, "Efficient Estimation ofDynamicPowerDissipation under a Real Delay Model", in Proceedings of IEEE International Conference on Computer-Aided Design, pp. 224-228, Nov., 1993

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E Rouatbi, B. Haroun and A. J. A1-Khalili, "Power Estimation Tool for Sub-Micron CMOS VLSI Circuits", in Proceedings of European Design Automation Conference, pp. 204-209, 1992

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C. Deng, "Power Analysis for CMOS/BiCMOS Circuits", in Proceedings of International Workshop on Low Power Design, pp. 3-8, April, 1994

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R. Marculescu, D. Marculescu and M. Pedram, "Logic level power estimation considering spatiotemporal correlations", in Proceedings of IEEE International Conference on Computer-Aided Design, pp. 294-299, Nov., 1994

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R. Marculescu, D. Marculescu and M. Pedram, "Efficient power estimation for highly correlated input streams", in Proceedings of the 32nd IEEE Design Automation Conference, pp. 628-634, June, 1995

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S. Rajgopal and G. Mehta, "Experiences with Simulation-Based Schematic Level Current Estimation", International Workshop on Low Power Design, pp. 9-14, April,1994

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Cited By

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Ayupov ABurns SPhillips JHu AGraeb H(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132480(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132480
Ayupov ABurns S(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105406(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105406
Pedram M(2009)Power Simulation and Estimation in VLSI CircuitsDesign Automation, Languages, and Simulations10.1201/9780203009284.ch11(11-1-11-27)Online publication date: 6-Nov-2009
https://doi.org/10.1201/9780203009284.ch11
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Index Terms

Improving the efficiency of power simulators by input vector compaction
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Ayupov ABurns SPhillips JHu AGraeb H(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132480(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132480
Ayupov ABurns S(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105406(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105406
Pedram M(2009)Power Simulation and Estimation in VLSI CircuitsDesign Automation, Languages, and Simulations10.1201/9780203009284.ch11(11-1-11-27)Online publication date: 6-Nov-2009
https://doi.org/10.1201/9780203009284.ch11
Marculescu RMarculescu DPedram M(2006)Sequence compaction for power estimationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.77117918:7(973-993)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.771179
Ramalingam NBhanja SLach JQu GIsmail Y(2005)Causal probabilistic input dependency learning for switching model in VLSI circuitsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057689(112-115)Online publication date: 17-Apr-2005
https://dl.acm.org/doi/10.1145/1057661.1057689
Chih-Yang Hsu Chien-Nan Jimmy Liu Jing-Yang Jou (2003)Improved vector compaction for power estimation with multi-sequence sampling technique2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)10.1109/VTSA.2003.1252581(176-179)Online publication date: 2003
https://doi.org/10.1109/VTSA.2003.1252581
Gopalakrishnan CKatkoori SGupta S(2003)Power optimisation of combinational circuits by input transformationsIEE Proceedings - Computers and Digital Techniques10.1049/ip-cdt:20030418150:3(133)Online publication date: 2003
https://doi.org/10.1049/ip-cdt:20030418
Chih-Yang Hsu Wen-Zen Shen (2002)Vector compaction for power estimation with grouping and consecutive sampling techniques2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)10.1109/ISCAS.2002.1011027(II-472-II-475)Online publication date: 2002
https://doi.org/10.1109/ISCAS.2002.1011027
Chih-Yang Hsu Chaur-Wen Wei Wen-Zen Shen (2001)A pattern compaction technique for power estimation based on power sensitivity informationISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)10.1109/ISCAS.2001.922086(467-470)Online publication date: 2001
https://doi.org/10.1109/ISCAS.2001.922086
Chaudhry RBlaauw DPanda REdwards TDe Micheli G(2000)Current signature compression for IR-drop analysisProceedings of the 37th Annual Design Automation Conference10.1145/337292.337362(162-167)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337362
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Static Compaction Techniques to Control Scan Vector Power Dissipation

Input Efficiency Measures: A Generalized, Encompassing Formulation

Improving Output Compaction Efficiency with High Observability Scan Chains

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Static Compaction Techniques to Control Scan Vector Power Dissipation

Input Efficiency Measures: A Generalized, Encompassing Formulation

Improving Output Compaction Efficiency with High Observability Scan Chains

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